A fine-grained timing driven synthesis of arithmetic circuits

Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic synthesisers, which play a fundamental role in design today, play a minor role on most arithmetic circuits, performing some local optimisations but hardly improving the overall structure of arithmetic components. Architectural optimisations have been often studied manually, and only in the case of very common building blocks such as fast adders and multi-input adders, ad-hoc techniques have been developed. A notable case is multi-input addition, which is the core of many circuits such as multipliers, etc. The most common technique to implement multi-input addition is using compressor trees, which are often composed of carry-save adders (based on (3 : 2) counters, i.e., full adders). A large body of literature exists to implement compressor trees using large counters. However, all the large counters were built by using full and half adders recursively. In this paper we give some definite answers to issues related to the use of large counters. We present a general technique to implement large counters whose performance is much better than the ones composed of full and half adders. Also we show that it is not always useful to use larger optimised counters and sometimes a combination of various size counters gives the best performance. Our results show 15% improvement in the critical path delay. In some cases even hardware area is reduced by using our counters.

In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.

High-speed full adder based on minority function and bridge style for nanoscale

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Subthreshold operating region of transistor shows huge potential toward satisfying demand of ultralow power (ULP) consumption from handheld portable devices. However, operating device with such small subthreshold leakage current as a switching current gives huge penalty in their operating frequency. For subthreshold operating region key design goal is to boost the speed of the device. DG FinFET device shows excellent device characteristics in subthreshold operating region. In this paper, 1-bit Full adder cell has been effectively analyzed. Since driving leakage current depends on operating temperature, performance analysis of Full adder is performed at different temperature. Simulation results show that dynamically connected static CMOS Full adder shows 43% advantage in delay over conv. static Full adder cell. DG FinFET-based Full adder cell shows significant advantage in delay as well as switching energy over static CMOS and DT CMOS-based Full adder.

Due to high power consumption and difficulties with minimizing the CMOS\ntransistor size, molecular electronics has been introduced as an emerging\ntechnology. Further, there have been noticeable advances in fabrication of\nmolecular wires and switches and also molecular diodes can be used for\ndesigning different logic circuits. Considering this novel technology, we use\nmolecules as the active components of the circuit, for transporting electric\ncharge. In this paper, a full adder cell based on molecular electronics is\npresented. This full adder is consisted of resonant tunneling diodes and\ntransistors which are implemented via molecular electronics. The area occupied\nby this kind of full adder would be much times smaller than the conventional\ndesigns and it can be used as the building block of more complex molecular\narithmetic circuits.\n

In recent decades, complementary metal–oxide–semiconductor (CMOS) downscaling has faced some serious challenges such as undesired leakage current densities and high power dissipation. One of the most attractive and promising alternative technologies to CMOS is nanomagnetic logic (NML), which is based on nonvolatile ferromagnetic computing states. In this paper, a novel full adder cell is suggested by providing a feedback loop to a special multilayer nanomagnetic majority voter, which switches between three- and five-input majorities periodically. This solution also represents an example revealing the potential of NML for circuit designs that are not accessible using other technologies such as CMOS or quantum-dot cellular automata (QCA). This capability comes from the combination of a clocking system and the nonvolatile behavior of NML. The correct operation of the new full adder cell is verified using the MQCA Verilog library. Comparisons with other state-of-the-art full adders show significant improvements in terms of density and simplicity.

VLSI computing is critical in chip fabrication in today's digital age. Moore's law demands that "the number of transistors on a microchip doubles every two years" in addition to that "the count of transistors employed in a chip size is reduced". As a result, this rule is dictating the electronics industry by reducing chip area, size, and power consumption while simultaneously enhancing chip fabrication strength. The arithmetic circuits are constructed in this work, by boosting the efficiency of circuits by considering die space as a constraint. Overall, arithmetic circuits have a bunch of usages in processing architecture. The XOR gate and multiplexer are utilized in this study to make compressor circuits more efficient by taking into account area, power, and delay. To examine the arithmetic circuit's performance, the load capacitance is customized and the power dissipation across the capacitor is studied.

The emerging of smart, battery operated, handheld mobile electronics (e.g., PDA, notebooks, mobile phones), and the widespread use of wireless sensor networks have raised the demand for ultra-low power electronics. The scaling of CMOS devices deep into the nano-regime brings promise for smaller, faster, and cheaper computing systems. However, it also leads to several challenges including power consumption and dynamic parameters fluctuations/variations, as well as intrinsic and extrinsic noises, with significant effects on the novel power-reliability tradeoff. This paper studies the effect of threshold voltage variations on the reliability of five full adder cells. It starts from the device-level by estimating the effects threshold voltage variations play on the reliability of scaled CMOS transistors. These estimations are then used to accurately calculate the reliability of the Sum and Carry-out signals of the five full adder cells under investigation. The simulation results show that the five full adders have reliabilities which are quite similar and mimic the reliability of the elementary devices, hence being strongly influenced by these.

This paper presents a comparative research of low-power and high-speed full adder cells which are based on XOR-XNOR algorithm. The adder cells are decomposed into small modules and all of them have an in-depth analysis. Several designs of each of them are implemented, optimized, simulated and analyzed separately. We also design a novel XORXNOR module built upon bootstrapped pass transistor logic use silicon on insulator (SOI) process with the characteristics of the full voltage swing at internal nodes and low shortcircuit current which helps in reducing the power-delay product (PDP) for high performance applications. Many different full adder cells are constructed with different XOR-XNOR modules. A realistic test environment with buffers and loads are used for simulation. All full adder cells were simulated by HSPICE based on 130 nm CMOS technology at 1.2 V supply voltages. Four sets of frequencies were operated: 25 MHz, 50 MHz, 100 MHz and 200 MHz with 50% duty cycle at four different load capacitances. A comprehensive comparison and analysis are also carried out to test the performance of the adders. Each of these cells shows different performances in terms of power consumption, speed, and PDP. The simulation results of this research are expected to help designers to select the appropriate full adder cell that satisfies their specific applications.

In this paper, single bit full adder hybrid circuit has been proposed which consist of two techniques i.e. Pass transistor Logic (PTL) and Gate Diffusion Technique (GDI). Several logic families are described by PTL which is utilized in the architecture of integrated circuits. PTL technique is used to decreases the number of transistors in the circuits to make different gates of logic by eradicating redundant transistors. GDI technique is utilized for the low power consumption. In this paper CADENCE VIRTUOSO tool is being used and all the simulation work is done on it by utilizing the technology node at 180nm along with a supply voltage of 1.8V. The simulation result represents that the proposed architecture of single bit hybrid full adder cell absorbs 53% less power in comparison with hybrid full adder [5], 5% less power in comparison with 3T XNOR [6], 58% less power in comparison with 8T full adder cell [6] and 86% less power in comparison with Adder using MDCVSL [8]. As we know that power and propagation delay both are varying inversely but still the propagation delay is not affected much and it is almost similar than the existing designs.

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90[Formula: see text]nm technology operating at 1.2[Formula: see text]V supply voltage and UMC 55[Formula: see text]nm CMOS technology operating at 1.0[Formula: see text]V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

Full adder can be designed using CMOS logic, transmission gates, dynamic logic or pass transistor logic. This paper presents Pass Transistor Logic based one bit full adders. The PTL based adder designs considered were SERF adder, 9A adder, 13A adder, CLRCL adder and 8T adder. Conventional 28T CMOS adder was also analysed. All the designs were simulated using Tanner EDA tool. Simulations were done at 180nm, 130nm and 90nm technologies. Transient analyses were done at frequencies ranging from 100MHz to 500MHz. The load capacitance was varied between 50fF to 250fF. Performance analyses were done with respect to power, delay and energy consumption obtained at 180nm, 130nm and 90nm technologies. At 180nm and 90nm, the 8T adder has lower power delay product (PDP). At 130nm 13A adder has got lower PDP when compared to all other adder designs. The 2bit, 4-bit and 8-bit ripple carry adders were designed at 180nm technology to analyse the performance in real time applications. 8T and 13A ripple carry adders were found to be the best with respect to delay and energy consumption respectively.

A low-power pseudo-dynamic full adder cell for image addition

Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.