A Time Varying Capacitance as Load to Study Area Efficient Arithmetic Circuits

Interconnect delays, bandwidth and power consumption are increasingly dominating IC performance due to increases in chip size and reduction in the minimum feature size, in spite of new materials like Cu with low-k dielectric. Thereby severely limiting chip performance unless a paradigm shift from present interconnect architecture is introduced. One such promising technique is three-dimensional (3-D) ICs with multiple active Si layers and vertical interconnects. This paper presents a comprehensive review of 3-D ICs with multiple semiconductor layers. It is shown that significant improvement in performance and reduction in wire-limited chip area can be achieved with 3-D ICs if some long horizontal interconnects can be replaced by short vertical inter-layer interconnects. We also address the thermal concerns due to increased power density for 3-D circuits. Finally, an overview of some of the processing techniques which can be used to fabricate these circuits, is reviewed.

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

Synthesizing a fast arithmetic circuit in high-speed systems is one of the most important design considerations. In particular, it is widely recognized that generating a parallel bit-level structure using full-adder (FA) cells as the design primitive is the most fine-grained and effective method of synthesizing fast arithmetic circuits in RTL synthesis. This work overcomes two inherent limitations of the previous methods of the fast FA-tree construction. Those are (1) the unawareness of slew rate at the input ports of FAs, and (2) the unawareness of load capacitance at the output ports of FAs, which are critically important for achieving a high accuracy of circuit timing estimation. Precisely, we show in this paper that considering the (possibly non-uniform) slew rate and load capacitance at the FA ports in estimating timing in the course of FA-tree construction greatly affects the latency of the resultant arithmetic circuit, and propose a slew rate and load-aware comprehensive FA-tree generation algorithm. We confirm the effectiveness of the proposed algorithm integrating a fine-grained FA timing model through experiments with diverse arithmetic designs commonly appeared in DSP and Multimedia applications. In summary, compared to the designs produced by the best ever known FA-tree synthesis method, our proposed synthesis algorithm is able to reduce the timing on average by 12% further.

Tremendous amounts of data are being generated and should be processed during the massive employment of artificial intelligence and edge/cloud computing, necessitating computers with higher capabilities. However, as Moore's Law approaches its limit, enhancing computing capability through transistor miniaturization is becoming less feasible. New strategies for “more-than-Moore” are highly preferred to drive future technological advancements. Multiple-valued logic, especially ternary logic with its superior data density compared to traditional binary logic, offers a viable route to augment computing capability while reducing chip interconnections and dynamic power consumption. Despite the growing interest in ternary logic within academia and industry, its practical application remains limited due to the increased transistor count and connections required by earlier logic gate implementations. In this thesis, we present efficient implementation methods of basic ternary logic gates based on emerging nano-electronics including two-dimensional material-based transistors. The fabricated ternary devices show high performance in DC gain and low power consumption. Additionally, compact models of the devices have been established and calibrated, facilitating the circuit design and simulation in Electronic Design Automation (EDA) tools. At the circuit level, this thesis introduces novel ternary arithmetic circuits, including adders and multipliers, that are optimized for low power consumption and minimal delay. Finally, we showcase the practical benefits of ternary logic systems in data processing through the implementation of carry-free arithmetic circuits, underscoring their potential as a transformative computing paradigm.

Bubble-to-bubble logic operations can greatly enhance the versatility of bubble memory devices. Our experience to date, however, has shown us that logic operations reduce the device operating margins to a degree that would allow logic only where the ratio of memory sites to logic gates is greater than one hundred. For example, quasistatic rotating field operation of exclusive OR, AND/OR, and replicate gates was obtained for a ± 3.5 percent bias margin at 45 to 55 Oe rotating field drive for an AND/OR gate to a ± 1.5 percent bias field margin at 50 to 60 Oe rotating field drive for an exclusive OR gate. In all cases these devices were prepared by ion milling or chemical etching T-bar, Y-bar, or chevron patterns in 3000 to 5000 A thick Permalloy films on glass. The pattern feature sizes ranged from 3 to 7.5 μm. The Permalloy on glass patterns were placed on epitaxially grown magnetic garnet wafers with bubble diameters ranging from 8 to 17 μm. Circuit operation was determined by visual observation. In all cases, the results are from either the first design of the circuits or the first iteration design.

Many difficulties have confronted the system-on-chip (SoC) industry during the previous ten years. These difficulties will likely become more significant as more and more applications revolve on the Internet of Everything (IoE). These issues include reducing power consumption for greater energy efficiency, overcoming numerous causes of variation to ensure reliable performance, and reducing design area to save money and boost integration. As a result, chip designers encounter various hurdles when attempting to create stable structures with complicated angles of capability while preserving a small die size and power expenditure. Memory components are among the most critical circuit components on every chip. They account for the majority of the chip's size and power consumption, which has an impact on the overall efficacy and reliability of the chip. These consist of a diverse multitude of serial elements in logic paths, caches, register files, and large memory arrays. In contemporary synchronized CMOS circuits, sequence elements are indispensable components. In fact, they can be responsible for up to 50% of the average number of cells in a semiconductor. We propose a novel methodology aimed at enhancing the reliability of pulsed latches while ensuring that there is no substantial decline in efficiency, area, or power consumption. Furthermore, given that sequential elements can be utilized in creating compact register files, the implementation of pulsed latches in register files is reviewed and compared with other conventional implementations, including static random-access memory (SRAM) and flip-flops. Also shown are new implementations of multiport register files, which are highly beneficial for many applications. The suggested approach has been proven to considerably decrease the enormous excess in area, power consumption, and latency that is typically associated with conventional methods of designing multiport register files

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.

Technical and economic factors have caused the field of physical design automation to receive increasing attention and commercialization. The steady down-scaling of complementary metal oxide semiconductor (CMOS) device dimensions has been the main stimulus to the growth of microelectronics and computer-aided very large scale integration (VLSI) design. The more an Integrated Circuit (IC) is scaled, the higher its packing density becomes. For example, in 2006 Intel's 65-nm process technology for high performance microprocessor has a reduced gate length of 35 nanometers. In their 70-Mbit SRAM chip, there are up to 0.5 billion transistors in a 110 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip size with 3.4 GHz clock speed. New technology generations come out every two years and provide an approximate 0.7 times transistor size reduction as predicted by Moore's Law. For the ultimate scaled MOSFET beyond 2015 or so, the transistor gate length is projected to be 10 nm and below. The continually increasing size of chips, measured in either area or number of transistors, and the wasted investment involving fabricating and testing faulty circuits, make layout analysis an important part of physical design automation. Layout-versus-schematic (LVS) is one of three kinds of layout analysis tools. Subcircuit extraction is the key problem to be solved in LVS. In LVS, two factors are important. One is run time, the other is identification correctness. This has created a need for computational intelligence. Fuzzy attributed graph is not only widely used in the fields of image understanding and pattern recognition, it is also useful to the fuzzy graph matching problem. Since the subcircuit extraction problem is a special case of a general-interest problem known as subgraph isomorphism, fuzzy attributed graphs are first effectively applied to the subgraph isomorphism problem. Then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the subcircuit extraction problem. Similarity measurement makes a significant contribution to evaluate the equivalence of two circuit graphs. To evaluate its performance, we compare fuzzy attributed graph approach with the commercial software called SubGemini, and two of the fastest approaches called DECIDE and SubHDP. We are able to achieve up to 12 times faster performance than alternatives, without loss of accuracy

Prior to 90nm the main contributor to yield loss was particle contamination. Random particle defects were directly proportional to particle density and chip size. To maximize yield, manufacturing was done in clean rooms where particles were reduced to a minimum. Yield was then directly proportional to the chip size. At 90nm and below, systematic defects play major roles in yield. Two designs of the same size can result in very different yield. This paradigm shift is caused by the printability problems that are inherent to process technologies operating in the sub-wavelength regime. The technology for printing patterns on silicon has not kept up with Moore's law. The wavelength of lithography equipment is as much as 6 times larger than the silicon features. This results in greater variation on silicon, which directly affects yield. How the design is implemented is becoming as important as how small you make it. Even at the standard cell level different solutions can demonstrate increased sensitivity to particles, short, opens, gate leakage and other yield issue. We present in this paper a methodology for grading how well standard cells will print on silicon. Using standard cell layouts, we predict a silicon image under different process conditions and take CD measurements on these images. These measurements are converted into a printability factor for each cell. This printability factor is used to grade cells and identify which cells have the largest impact on printability and which should be optimized. To help with this optimization the measurements are also used to mark printability hot spots in the cell layouts.

In this paper, the thermal performance analysis and optimization of the package of a specific multi-heat source power device is carried out. Firstly, the finite element analysis software ANSYS Icepak is used as a tool to build a simplified model of the array type multi-power device package module. Secondly, the impact of five variable parameters on thermal performance of multi-heat source power devices is analyzed. These parameters are chip size, chip power consumption, die attach material, packaging material, package size. Finally, through the orthogonal test analysis method, the junction temperature and thermal resistance of the package are selected as the test indexes, and five parameters are selected as the orthogonal test factors to analyze the influence of the five parameters on the thermal performance. The results show that the thermal conductivity of the die attach material is most significant regardless of the package junction temperature or thermal resistance. By summarizing the influence of various factors on the thermal performance of power devices, the suggestions for optimizing the thermal performance of multi-heat source power devices are proposed. The results obtained have important guiding significance for the thermal performance optimization of power devices.

This work describes a novel fully integrated rectenna circuit using tunnelling-based devices for implanted medical devices. An ASPAT (Asymmetric Spacer Layer Tunnel Diode) was used as the active rectifier due to its high non-linearity and temperature insensitivity features. A miniaturized geometry rectenna ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 \times 5$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) with improved matching characteristics was demonstrated, by integrating a Cockcroft-Walton rectifier with an L-shaped planar folded antenna structure operating at ISM frequency bands. The circuit performance was experimentally explored at various separation distance between transmitter and receiver units. For a 5cm transmission set-up, the rectenna with a single-stage rectifier delivered 0.8V output at 20dBm transmit power. An extended doubler configuration exhibited enhanced performance when multiple stages are used, is predicted to reach 0.24mW output power at 23dBm transmit power and yielding ~1.6V output voltage with an efficiency of 0.12%. These findings can assist in compensating for the degraded antenna gain attributed to the extremely small effective-radiating area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.04\lambda $ </tex-math></inline-formula> . Furthermore, the ability of controlling the antenna input impedance helps in circumventing the requirement for a matching circuitry thereby offering further reduction in chip size.

In this study, a new clock and ramp generator circuit framework with a 0.9V low operational voltage is designed for the voltage-mode/current-mode-controlled power management integrated chip of a DC-DC converter. In conventional clock and ramp generator circuit with operational amplifiers, its operational voltage is limited to be over 1.5V because of the problem of a higher threshold voltage in the metal-oxide-semiconductor field-effect transistor (MOSFET). As a result, it can not work well for a pulse-width-modulation DC-DC converter when a below 1V low-voltage single-cell clean-energy power source is applied. This newly-design clock and ramp generator circuit framework without operational amplifiers is investigated to cope with the limitation of the threshold voltage in the MOSFET. Therefore, the corresponding chip size and power consumption can be reduced. Moreover, this circuit still has the functions of adjustable clock frequency and ramp slope. In addition, numerical simulations by the HSPICE software and experimental results by a real chip fabricated in the TSMC 1P6M 0.18µm CMOS process are given to verify the effectiveness of the proposed circuit to produce the clock and ramp waveforms.

This paper describes a novel current driving circuit for an active matrix organic light emitting diode (AMOLED). The proposed current driving circuit has a lower power consumption and higher chip density for the AMOLED display compared with the conventional one because all elements operate at a normal voltage and are shielded from the high voltage of the panel. The chip size and power consumption of the current driving circuit for an AMOLED can be improved by about 30 to 40% and 10 to 20%, respectively, compared with the conventional one.

A new high-speed successive approximation analog-to-digital converter architecture is presented. Two bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two DACs, is another novelty of the new architecture. The simulation results for the designed 10-bit ADC show that in same conversion rate, better figure of merit value, 40% and 7% reduction in chip size and power consumption is achievable over the conventional SA-ADC architecture.

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