Device implementation and arithmetic circuit design of ternary logic

Traditional digital circuits use binary logic for implementation which requires more number of data lines to carry information. In contrast to binary, multiple-valued logic (MVL), digital circuits require less number of data lines to represent information. MVL uses more than two levels to represent a number; thereby reducing the number of interconnects. One of its kind is ternary logic, (known as radix-3 system) and uses three different voltage levels, whereas the other quaternary logic (radix-4 system) uses four different voltage levels to represent a number. Various digital circuits are implemented using MVL which potentially reduces the chip area, power consumption, and propagation delay. This article discusses about fundamental concepts of ternary, quaternary system and reviews some of arithmetic and logic circuits using ternary and quaternary logic. This paper also presents different methodologies used to implement arithmetic and logic operations using MVL. It is found that, due to the effective utilization of interconnects, MVL digital circuits provide better performance over binary digital circuits in terms of area, power, and delay.KeywordsNumber systemArithmetic and Logic circuitsChip areaMultiple-Valued Logic (MVL)Quaternary logicTernary logicTiming delayVLSI

In modern IC design, circuit designers often need to manually operate and move data among different EDA (Electronic Design Automation) tools. If these tools were installed in separate computers, due to the license and system requirements, the design flow will be frequently interrupted, to handle the dreary data movement work, and the design efficiency will thus be reduced. To alleviate the above problem, a seamless and efficient design flow would be a must. The aim of this paper is to propose a service-oriented integrated EDA environment that can improve the smoothness of the design flow and consequently increase the overall design productivity. In our approach, a multi-agent framework based on JADE platform is used to manage distributed EDA tools, which are encapsulated as agent services. Mobile agents are allowed to autonomously and concurrently migrate among computers to access services for IC designers. To facilitate that, a scripting language is designed for mobile agents to allocate tasks, cooperate with each other, and select appropriate services. To demonstrate the feasibility of our method, an Integrated Circuit Design Cycle Assistant System (ICDCAS) for simplifying the manual operations in IC design cycles is developed by combining two EDA tools: ModelSim and Xilinx ISE. The implemented system proves to have the features of time saving and being free of mistakes incurred by manually operating and configuring the sophisticated EDA tools.

Many-valued logics in general and 3-valued logic in particular is an old subject which had its beginning in the work of Łukasiewicz [Łuk]. Recently there is a revived interest in this topic, both for its own sake (see, for example, [Ho]), and also because of its potential applications in several areas of computer science, such as proving correctness of programs [Jo], knowledge bases [CP] and artificial intelligence [Tu]. There are, however, a huge number of 3-valued systems which logicians have studied throughout the years. The motivation behind them and their properties are not always clear, and their proof theory is frequently not well developed. This state of affairs makes both the use of 3-valued logics and doing fruitful research on them rather difficult.Our first goal in this work is, accordingly, to identify and characterize a class of 3-valued logics which might be called natural. For this we use the general framework for characterizing and investigating logics which we have developed in [Av1]. Not many 3-valued logics appear as natural within this framework, but it turns out that those that do include some of the best known ones. These include the 3-valued logics of Łukasiewicz, Kleene and Sobociński, the logic LPF used in the VDM project, the logic RM3 from the relevance family and the paraconsistent 3-valued logic of [dCA]. Our presentation provides justifications for the introduction of certain connectives in these logics which are often regarded as ad hoc. It also shows that they are all closely related to each other. It is shown, for example, that Łukasiewicz 3-valued logic and RM3 (the strongest logic in the family of relevance logics) are in a strong sense dual to each other, and that both are derivable by the same general construction from, respectively, Kleene 3-valued logic and the 3-valued paraconsistent logic.

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.

The rapid growth of the intergraded circuit industry as predicted by Moores law has significantly increased the importance of efficient design processes. In addition, due to physical constraint, we will soon reach the limit of how small the size of the transistor can become, and the design processes will become more complex than ever. In order to cope with those challenges and introduce the product to the market within the time to market, the industry has been developing ways to apply machine learning to concurrent EDA tools. This paper will aim to introduce how machine learning is applied to varies processes of electronic design and how they improve the current EDA tools. We will also show the limitations and opportunities of ML based EDA tools and provide a rough idea of the potential future to those who are looking into this area.

Provision of free, downloadable industry-standard reconfigurable hardware EDA tools is a growing and welcome trend. Low cost, ever-more-complex FPGA-based embedded system development platforms with host interface control are becoming more readily available. This paper describes a series of structured VHDL workshop modules which use the Xilinx ISE Webpack/ModelsimXE electronic design automation (EDA) tools and Digilent Spartan-3 hardware development system. The described course implements an extendable embedded system, which performs a selection of image and audio processing applications, controlled by a host graphical user interface (GUI). A formal structured design, documentation and test methodology is incorporated throughout the course. Enhancements to EDA tool VHDL and diagram creation wizard support are proposed to aid VHDL capture automation and design visualisation. Improved student understanding and achievement level in VHDL programming, digital embedded system design techniques and FPGA implementation has resulted

With Moore's law in effect, as the complexity of digital electronic circuits increases, the amount of time spent by the electronic design automation (EDA) tools to design such circuits also increases. It brings us to the point, where we need to improve the performance of EDA algorithms to fulfil the present and the future requirements of the EDA industry. Out of many algorithms used by these tools, Breadth First Traversal (BFT) is one of the most commonly used algorithms to traverse the gates of electronic circuits. In this paper, we present a new simple, fast and parallelizable BFT algorithm for sparse graphs, named H-BFT. We show that the CPU implementation of H-BFT is about 75× faster than the CPU implementation of the state of the art, the Sparse Matrix-Vector Product (SMVP) based BFT. Further, with the new features introduced by NVIDIA in their GPUs, we have accelerated both the state of the art SMVP based BFT implementation and our new H-BFT implementation. The best speedups we achieved via these accelerations are 180× and 25× for the SMVP-BFT and H-BFT respectively.

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low‐complex, high‐speed, and energy‐efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi‐threshold graphene nanoribbon field‐effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET‐based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

Recent developments in EDA tools for power electronics modules have led to simultaneous analysis and optimization of package features with regard to electro-thermal and thermo-mechanical aspects. In this work, two of these EDA tools, PowerSynth and ParaPower, are linked together with a software application programming interface (API) to rapidly explore a combined electro-thermo-mechanical design space and present the user with co-optimized solutions and tradeoffs in a fraction of the time consumed using traditional analysis methods. An overview of this co-design process and its advantages over that of the traditional, iterative approach is presented along with an explanation of the methods used by the respective tools for analysis. Finally, additional considerations and constraints are introduced that ensure manufacturing feasibility and reliable operation at high voltages. A case study in co-design using these tools has been proposed for the final paper.

Advanced electronic design automation (EDA) tools, with their simulation, modeling, design rule checking, and optical proximity correction capabilities, have facilitated the improvement of first pass wafer yields. While the data produced by these tools may have been processed for optimal wafer manufacturing, it is possible for the same data to be far from ideal for photomask manufacturing, particularly at lithography and inspection stages, resulting in production delays and increased costs. The same EDA tools used to produce the data can be used to detect potential problems for photomask manufacturing in the data. A production implementation of automated photomask manufacturing rule checking (MRC) is presented and discussed for various photomask lithography and inspection lines. This paper will focus on identifying data which may cause production delays at the mask inspection stage. It will be shown how photomask MRC can be used to discover data related problems prior to inspection, separating jobs which are likely to have problems at inspection from those which are not. Photomask MRC can also be used to identify geometries requiring adjustment of inspection parameters for optimal inspection, and to assist with any special handling or change of routing requirements. With this foreknowledge, steps can be taken to avoid production delays that increase manufacturing costs. Finally, the data flow implemented for MRC can be used as a platform for other photomask data preparation tasks.

In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. 
 Keywords: Ternary logic, Ternary logic gates, VHDL language.

Digital Electronic Design Automation (EDA) tools have seen a remarkable improvement over the last decade. In addition to providing good documentation, their ability to simulate a design provides immense convenience in optimizing a design and in examining what-if scenarios which would otherwise be very time-consuming, expensive, and even impossible using hardware. This paper begins with an overview of EDA tools and related issues. Next, it discusses the implementation of an EDA laboratory established with funding from the National Science Foundation. Details of four experiments and an evaluation of the EDA tools used in the undergraduate curriculum have been presented.

Over the past decade, CMOS scaling has seen increasingly intrusive challenges from cost, variability, energy, reliability, and fundamental device-architectural and materials limitations. To maintain Moore's-Law scaling of integration value, the industry is urgently exploring beyond-silicon and beyond-CMOS device, interconnect and memory options, as well as heterogeneous, More than Moore integration and packaging technologies. This coincides with a turning point for the Electronic Design Automation (EDA) field, which has for 50+ years been a key enabler of the semiconductor industry's amazing growth. Maturation of the EDA industry and its related academic research efforts inevitably result in a spiral of declining valuations (multiples), venture capital investments, research funding, and student interest. To counter this trajectory, the EDA field's business models, research portfolios, and funding models have been going through various diversifications, but in a rather ad-hoc manner. This begs the question of how the paradigms and research methodologies of EDA can be leveraged for design automation (DA) in other, emerging domains. Arguably, more efficient evolution and growth as a community requires a more systematic, coherent effort -- as well as forward-looking vision -- to steer by. In this paper, we review initial efforts of a new IEEE CEDA technical activity group dedicated to this purpose. These efforts span the cataloguing of past and current research trends, development of new metrics of research impact, and visions for future applications of EDA paradigms in broader design automation contexts. It is hoped that these efforts will be useful to the EDA community as it continues to evolve beyond its E-roots.

New complex and Low Power systems are being implemented using advanced Electronic Design Automation (EDA) tools. Low power designs are not only used in small size applications like mobile phones, tablets and handheld devices but also in high-performance computing applications. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the synchronous circuit. In the research of low power and low voltage VLSI circuits, the use and implementation of Dual Edge Triggered Flip-Flop (DETFF) has gained more attention at the gate level design. The main advantage of using DETFF is that it allows one to maintain a constant throughput while operating at only half the clock frequency. In this paper, a dual-edge triggered sense amplifier flip-flop is designed for low power systems. For DETFF, the optimal delay, power consumption, and energy are determined as the primary figures of merit. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed.

Fault injection attacks have become a serious threat against cryptographic ICs. The existing countermeasures rely on error detection and correction, which brings a large area and power overhead. This paper proposes a security enhancement design method against fault injection attacks, which selectively protects or detects only the vulnerable logic cells in a cryptographic circuit. These vulnerable cells of the cryptographic ICs can be accurately identified on the system level and the security enhancement will be conducted only on these cells on the circuit level. This security enhancement design method has the advantages of smaller area and power overheads, transparency to the IC designers and compatibility to the common electronic design automation (EDA) tools.