Natural 3-valued logics—characterization and proof theory

Traditional digital circuits use binary logic for implementation which requires more number of data lines to carry information. In contrast to binary, multiple-valued logic (MVL), digital circuits require less number of data lines to represent information. MVL uses more than two levels to represent a number; thereby reducing the number of interconnects. One of its kind is ternary logic, (known as radix-3 system) and uses three different voltage levels, whereas the other quaternary logic (radix-4 system) uses four different voltage levels to represent a number. Various digital circuits are implemented using MVL which potentially reduces the chip area, power consumption, and propagation delay. This article discusses about fundamental concepts of ternary, quaternary system and reviews some of arithmetic and logic circuits using ternary and quaternary logic. This paper also presents different methodologies used to implement arithmetic and logic operations using MVL. It is found that, due to the effective utilization of interconnects, MVL digital circuits provide better performance over binary digital circuits in terms of area, power, and delay.KeywordsNumber systemArithmetic and Logic circuitsChip areaMultiple-Valued Logic (MVL)Quaternary logicTernary logicTiming delayVLSI

In the paper we explore the idea of describing Pawlak’s rough sets using three-valued logic, whereby the value t corresponds to the positive region of a set, the value f — to the negative region, and the undefined value u — to the border of the set. Due to the properties of the above regions in rough set theory, the semantics of the logic is described using a non-deterministic matrix (Nmatrix). With the strong semantics, where only the value t is treated as designated, the above logic is a “common denominator” for Kleene and Łukasiewicz 3-valued logics, which represent its two different “determinizations”. In turn, the weak semantics—where both t and u are treated as designated—represents such a “common denominator” for two major 3-valued paraconsistent logics.

Tremendous amounts of data are being generated and should be processed during the massive employment of artificial intelligence and edge/cloud computing, necessitating computers with higher capabilities. However, as Moore's Law approaches its limit, enhancing computing capability through transistor miniaturization is becoming less feasible. New strategies for “more-than-Moore” are highly preferred to drive future technological advancements. Multiple-valued logic, especially ternary logic with its superior data density compared to traditional binary logic, offers a viable route to augment computing capability while reducing chip interconnections and dynamic power consumption. Despite the growing interest in ternary logic within academia and industry, its practical application remains limited due to the increased transistor count and connections required by earlier logic gate implementations. In this thesis, we present efficient implementation methods of basic ternary logic gates based on emerging nano-electronics including two-dimensional material-based transistors. The fabricated ternary devices show high performance in DC gain and low power consumption. Additionally, compact models of the devices have been established and calibrated, facilitating the circuit design and simulation in Electronic Design Automation (EDA) tools. At the circuit level, this thesis introduces novel ternary arithmetic circuits, including adders and multipliers, that are optimized for low power consumption and minimal delay. Finally, we showcase the practical benefits of ternary logic systems in data processing through the implementation of carry-free arithmetic circuits, underscoring their potential as a transformative computing paradigm.

Minimal Herbrand models of sets of first-order clauses are useful in several areas of computer science, for example, automated theorem proving, program verification, logic programming, databases, and artificial intelligence. In most cases, the conventional model generation algorithms are inappropriate because they generate nonminimal Herbrand models and can be inefficient. This article describes an approach for generating the minimal Herbrand models of sets of first-order clauses. The approach builds upon i>positive unit hyperresolution (i>PUHR) i>tableaux, that are in general smaller than conventional tableaux. PUHR tableaux formalize the approach initially introduced with the theorem prover SATCHMO. Two minimal model generation procedures are described. The first one expands PUHR tableaux depth-first relying on a i>complement splitting expansion rule and on a form of backtracking involving constraints. A Prolog implementation, named MM-SATCHMO, of this procedure is given, and its performance on benchmark suites is reported. The second minimal model generation procedure performs a breadth-first, constrained expansion of PUHR (complement) tableaux. Both procedures are optimal in the sense that each minimal model is constructed only once, and the construction of nonminimal models is interrupted as soon as possible. They are complete in the following sense: The depth-first minimal model generation procedure computes all minimal Herbrand models of the considered clauses provided these models are all finite. The breadth-first minimal model generation procedure computes all finite minimal Herbrand models of the set of clauses under consideration. The proposed procedures are compared with related work in terms of both principles and performance on benchmark problems.

In terms of memory, multivalued logic can be the fitting logic for the existing binary logic. Ternary logic contains three symbols in place of two symbols used in the binary logic, i.e., 0, 1, 2. More information can be stored with the help of these three symbols. SRAM cell is widely used in the digital circuit. The SRAM cell designed using the ternary logic can be used in the design of large memory arrays designed using ternary logic. The traditional ternary inverter which is used in the design of the traditional ternary SRAM cell is unable to store the proper values for the second state, there is a voltage level drop, which in turn affects the data read/write value of the SRAM cell designed using this traditional ternary inverter. Hence there is a need to design the ternary inverter cell which can give the proper output voltage level of all three states of the ternary logic. The level shift ternary inverter is designed to fulfill this disadvantage. The ternary inverter is designed in order to achieve the ideal DC characteristics, and the same level shift ternary inverter is used in the design of level shift ternary SRAM. This ternary SRAM stores the data properly at read/write signal. The traditional ternary inverter and traditional ternary SRAM, level shift ternary inverter and level shift ternary SRAM are implemented in Cadence 45 nm technology. The traditional ternary inverter consumes 2.37 μW power, and the level shift ternary SRAM consumes 2.43 μW power. The traditional ternary SRAM consumes 3.012 μW and level shift ternary SRAM consumes 3.14 μW. At the cost of a little bit increased power and the number of transistors, the traditional ternary SRAM can be replaced with level shift ternary SRAM. This level shift ternary SRAM stores all the voltage levels at all three levels. The same level shift ternary SRAM cell can be used for the design of large memory arrays.

The past few decades have seen a resurgence of reasoning techniques in artificial intelligence involving both classical and non-classical logics. In his paper, ``Multi-valued Logics: A Uniform Approach to Reasoning in Artificial Intelligence'', Ginsberg has shown that through the use of bilattices, several reasoning techniques can be unified under a single framework. A bilattice is a structure that can be viewed as a class of truth values that can accommodate incomplete and inconsistent information and in certain cases default information. In bilattice theory, knowledge is ordered along two dimensions: truth/falsity and certainty/uncertainty. By defining the corresponding bilattices as truth spaces, Ginsberg has shown that the same theorem prover can be used to simulate reasoning in first order logic, default logic, prioritized default logic and assumption truth maintenance system. Although this is a significant contribution, Ginsberg's paper was lengthy and involved. This paper summarizes some of the essential concepts and foundations of bilattice theory. Furthermore, it discusses the connections of bilattice theory and several other existing multi-valued logics such as the various three-valued logics and Belnap's four-valued logic. It is noted that the set of four truth values in Belnap's logic form a lattice structure that is isomorphic to the simplest bilattice. Subsequently, Fitting proposed a conflation operation that can be used to select sub-sets of truth values from this and other bilattices. This method of selecting sub-sets of truth values provides a means for identifying sub-logic in a bilattice.

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.

As the process of authentication and/or authorization becomes complicated, it is natural that more complicated structure of evidence is required to authenticate and/or authorize. Furthermore, an evaluation process may generate another process such as suspension with advice of additional evidence collection. In this paper, we propose using documents as evidence to authorization, and using Belnap logic in the evaluation process. Belnap logic is a multi-valued logic system that has been investigated to augment evaluation logics. By using Belnap logic in authorization, evaluation of evidence (document) for the authorization policy may generate a value ⊤ (conflict) or ⊥ (lack of evidence) in addition to true and false, which leads to an additional process of evidence completion. By this augmentation, more flexible and continuous authorization with advice for evidence completion is enabled. We prove that the evaluation of documents for a given policy in Belnap logic distinguishes the possibility of interactive and continuous improvement from simple failure.

In this chapter, a new type of combinational logic circuit realization is presented. These logic circuits are based on non-DC representation of logic values . In this scheme, logic values can be represented by signals that are uncorrelated, for example, distinct values represented by independent stochastic processes (noise from independent sources). This provides a natural way of implementing multivalued logic . Signals driven over long distances could take advantage of this fact and can share interconnect lines. Alternately, sinusoidal signals can be used to represent logic values. Sinusoid signals of different frequencies are uncorrelated. This property of sinusoids can be used to identify a signal without ambiguity. This chapter presents a logic family that uses sinusoidal signals to represent logic 0 and logic 1 values. We present sinusoidal gates which exploit the anti-correlation of sinusoidal signals, as opposed to uncorrelated noise signals. This is achieved by employing a pair of sinusoid signals of the same frequency, but with a phase difference of 180°. Recent research in circuit design has made it possible to harvest sinusoidal signals of the same frequency and 180° phase difference from a single resonant clock ring , in a distributed manner. Another advantage of such a logic family is its immunity from external additive noise. The experiments in this chapter indicate that this paradigm, when used to implement binary valued logic, yields an improvement in switching (dynamic) power.

The quest for efficient technologies beyond the traditional CMOS (Complementary-Metal-Oxide-Semiconductor) technology has led researchers to explore newer technologies like the CNFET(Carbon-Nanotube-Field-Effect-Transistor). CNFETs are being used to design and implement various ternary logic circuits. Multivalued logic (MVL) requires multiple threshold voltages that are possible to obtain using CNFETs by modifying the physical dimensions of their CNTs (Carbon Nano Tubes). The ternary sequential logic circuits like ternary D-latch, D-flipflop, and counters existing in literature have been implemented either using STIs (Standard Ternary Inverters) or successor-predecessor circuits. This paper proposes a new design methodology for a ternary D-flipflop that uses a ternary buffer and two STIs designed using two power supplies. Two hybrid architectures for ternary D-flipflop designs have also been proposed that are implemented using a combination of ternary buffer, STIs and successor-predecessor circuits. Using these ternary D-flipflop designs, ternary 3- trit synchronous and asynchronous counters are designed in this paper. The proposed designs are simulated using HSPICE and a standard Stanford CNFET model. The proposed ternary D-flipflops show an improvement of up to 93.5% in power, up to 44.7% in delay and up to 94.3% in PDP compared to existing designs.

Tiling theory is an elegant branch of mathematics that has applications in several areas of computer science. The most immediate application area is graphics, where tiling theory has been used in the

Graph repair, restoring consistency of a graph, plays a prominent role in several areas of computer science and beyond: For example, in model-driven engineering, the abstract syntax of models is usually encoded using graphs. Flexible edit operations temporarily create inconsistent graphs not representing a valid model, thus requiring graph repair. Similarly, in graph databases—managing the storage and manipulation of graph data—updates may cause that a given database does not satisfy some integrity constraints, requiring also graph repair.

With the spreading of Industry 4.0, cyber-physical systems, and tools for augmented and virtual reality, Digital Twin (DT) is gaining momentum in several areas of Computer Science and Engineering. This paper presents a systematic literature review that investigates the way DTs are described in Human-Computer Interaction (HCI) scientific literature. The study includes 23 papers selected through a systematic search on the 21 most ranked journals and conferences in the HCI area. As a result of this work, it appears clear that the way humans interact with DTs is a topic still far from being widely studied. A set of hints for future research about the relationship between HCI and DT constitute the main outcome of this paper.

Developments in several areas of computer science, robotics, and social robotics make it seem likely that a universal robot will be available in the foreseeable future. Large language models for communication, perception, and control play a central role in this. This article briefly outlines the developments in the various areas and uses them to create the overall image of the universal robot. It then discusses the associated challenges from an ethical and social science perspective. It can be said that the universal robot will bring with it new possibilities and will perhaps be one of the most powerful human tools in physical space. At the same time, numerous problems are foreseeable, individual, social, and ecological.

Herbrand models for clausal theories are useful in several areas of computer science. In most cases, however, the conventional model generation algorithms are inappropriate because they generate nonminimal Herbrand models and can be inefficient. This article describes a novel approach for generating minimal Herbrand models of clausal theories. The approach builds upon positive unit hyperresolution (PUHR) tableaux, that are in general smaller than conventional tableaux. To generate only minimal Herbrand models, a complement splitting expansion rule and a specific search strategy are applied. The proposed procedure is optimal in the sense that each minimal model is generated only once, and nonminimal models are rejected before their complete construction. First measurements on an implementation point to its efficiency.