Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach

In the last forty years the semiconductor industry focused on the downscaling process of the CMOS (Complementary Metal-Oxide-Semiconductor) technology, trying to follow as much as possible the empirical Moore's Law. In the last five years this trend has been facing technology limits that have led to the development of a new research field, named Beyond CMOS, which investigates new electron devices concept and materials that can replace or co-integrate the standard technology, to make large scale integrated (LSI), high performance, low power devices. Carbon nanotubes (CNTs) are considered one of the most promising materials for Beyond CMOS devices, both at front-end and back-end level. The development of the research on this new organic material is due to its nanometer scale dimensions and to its outstanding electrical (metallic and semiconducting behavior, ballistic conduction, current density > 109 A/cm2) and mechanical (Young's modulus ∼1 TPa) properties, nevertheless due to its low mass (mass density ρ = 1300 kg/m3). Among the several CNT applications already reported in literature (interconnections, sensors, transistors, memory, etc.), a particular interest is on their use to build Nano-Electro-Mechanical (NEM) devices, such as resonators and switches. NEM relays based on carbon nanotubes show large-current density drive and high speed operation compared to metal-based NEMS counterparts, low actuation voltage and low power, performances which are promising for radio-frequency (RF) applications, where RF MEM devices are considered as replacement solution for their off-chip and/or solid-state counterparts in front-end transceivers. Most of the previously reported CNT NEM switches concerns relay configuration based on one single movable nanotube and its DC characterization. Despite individual proof-of-concept merits, an electromechanical switch based on a single CNT usually presents an output signal level that is too low for practical applications and a poor reliable fabrication process, which opposes the precise control at wafer level achieved by standard technology. Alternatively, a very large-scale integration of NEM devices requires the exploitation of high-density aligned arrays of nanotubes, grown in precise locations and that could be patterned into well-defined and controlled configurations. The objective of this research work was to develop LSI NEM switches based on high dense carbon nanotube arrays in the back end of the line (BEOL), with conductive and capacitive contacts and tested from DC up to high frequency (RF), in order to evaluate their performances in a wide range of operations. The synthesis process of carbon nanotubes was performed by thermal CVD and temperature, gas concentration and catalyst pretreatment were optimized to achieve high dense aligned CNT arrays. A study on the catalyst geometries and on the substrate materials were performed in order to obtain horizontal aligned arrays grown directly on metallic substrate without density change. We developed a novel surface micromachining process to suspend CNT arrays. The DC characterization of CNT NEM switches was exploited to extract the equivalent electromechanical properties of the CNT membranes, since they behave as a new body material. We extracted an equivalent flexural modulus of 8.5 GPa and a resistivity of 0.0077 Ωcm. The devices, in both configurations, present a very low actuation voltage, below 10 V, lower than typical metal NEM switch for the same dimensions and a comparable switching time. The RF characterization was performed in the telecommunication frequency range (up to 6 GHz) showing reasonably high isolation and low insertion loss. The relay shows a lower reliability than the capacitive switch, due to the elevated drive current which induces the CNTs burning at the metal-to-metal interface. The RF measurements were used to extract the parameters of the proposed devices equivalent lumped model. Several implementations of CNT NEM switches, both for DC (reconfigurable interconnects, logic functions, memories) and RF (signal routing purposes in RF system Front-Ends, phase shifting networks or digitalized capacitor banks) applications, were reported.

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Although sorting networks have extensively been reported in literature (Batcher, 1962), there are a few references that cover a detailed explanation about their VLSI (Very Large Scale of Integration) realization in CMOS (Complementary Metal-Oxide-Semiconductor) technology (Turan et al., 2003). From an algorithmic point of view, a sorting network is defined as a sequence of compare and interchange operations depending only on the number of elements to be sorted. From a hardware perspective, sorting networks can be visualized as combinatorial circuits where a set of denoted compare-swap (CS) circuits can be connected in accordance to a specific network topology (Knuth, 1997). In this chapter, the design of sorting networks in CMOS technology with applicability to VLSI design is approached at block, transistor, and layout levels. Special attention has been placed to show the hierarchical structure observed in sorting schemes where the so called CS circuit constitutes the fundamental standard cell. The CS circuit is characterized through SPICE simulation making a particular emphasis in the silicon area and delay time parameters. In order to illustrate the inclusion of sorting networks into specific applications, like signal processing and nonlinear function evaluation, two already reported examples of integrated circuit designs are provided (Agustin et al., 2011; Jimenez et al., 2011).

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), ...

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and higher due to the enhancement of the short channel effect of transistors. CMOS Buffer is a very common circuit unit in VLSI. In this paper, a Pileup effect transistor (PET) is proposed to reduce the subthreshold leakage current of the CMOS buffer. The main principle of PET technology is to reduce the voltage difference between gate and source and the voltage difference between drain and source by lowering the voltage of source so as to reduce the subthreshold leakage current. Through simulation-based on Cadence and Taiwan Semiconductor Manufacturing Company (TSMC) N65 library, PET technology can reduce leakage current power consumption by about one-twelfth of the original while maintaining the function of the original CMOS buffer. PET technology has also been found to reduce current consumption in the transition state by about 40%.

Latch-up in CMOS (Complementary Metal-Oxide-Semiconductor) technology is a significant reliability concern in VLSI (Very Large Scale Integration) design. Latch-up is a parasitic, unintended creation of a low-impedance path between the power supply rails due to the triggering of parasitic thyristor structures inherent in CMOS processes. This phenomenon can lead to device malfunction, excessive current flow, and potential permanent damage to the integrated circuit. The impact of latch-up is profound, as it compromises the stability and functionality of electronic systems, especially in high-performance and high-reliability applications such as aerospace, medical devices, and critical infrastructure. The primary factors contributing to latch-up include high current spikes, radiation exposure, and improper circuit layout. Preventive measures are essential to mitigate these risks and ensure the robustness of CMOS circuits. Effective prevention strategies include the use of guard rings, which isolate the sensitive regions of the chip and prevent the formation of parasitic paths. Proper substrate doping and well design can also minimize latch-up susceptibility. Additionally, optimizing the layout design to minimize the proximity of p-n junctions and employing advanced CMOS processes with latch-up resistant technologies are crucial. This abstract highlights the importance of understanding and preventing latch-up in CMOS VLSI design to enhance the reliability and performance of modern integrated circuits.

: This report describes techniques for very large scale integration (VLSI) implementation of arithmetic algorithms. The report describes an algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root. Keywords include: Very large scale integration (VLSI); and Floating point chip design.

We propose a broad-based target classifier that recognizes a target on the principle of pattern matching based on associative memory, and can be implemented in hardware with standard complementary metal-oxide semiconductor (CMOS) cells. A major drawback in the field of neural networks is the inability to implement network designs in hard- ware inexpensively. Here we have designed an associative RAM-net memory neural classifier, which is based on the associative memory model of a winner-take-all classifier. In this model extensive use of ordi- nary random access memory is made. The benefit of this approach is that the entire architecture can be designed with current CMOS standard cells application-specific integrated circuit (ASIC) technologies as op- posed to current analog very large scale integration (VLSI) approaches. Since RAM can be easily added using the standard cell ASIC approach, a low-cost implementation for a wide variety of neural classification prob- lems is provided. The integration of all necessary features on a single chip results in an easily implementable, low-chip-count classification sys- tem. A full gate-level design of the architecture is created and simulated using the VHDL hardware programming language (Navabi, 1993; Mentor Graphics, 1992). The results are very encouraging, and warrant further research into various memory types and configurations. © 1998 Society of Photo-Optical Instrumentation Engineers. (S0091-3286(98)00507-8) Subject terms: target classifier; neural networks; associative memory; RAM-net memory.

Chapter 1 - Impact of VLSI on Computer Architectures

CMOS transistors with a 50 nm physical gate length are demonstrated. Super-halo, implemented by angle-tilted implantation, is utilized to control V/sub th/ roll-off down to a gate length of 40 nm. Super-halo also provides V/sub th/ adjustment as well as a retrograde channel to suppress subsurface body punch-through. 935 /spl mu/A//spl mu/m and 395 /spl mu/A//spl mu/m on-state drive currents were achieved for n- and p-channel MOSFETs, respectively, with a V/sub dd/ of 1.5 V. The I/sub drive//(C/sub ox(inv)/V/sub dd/) figure-of-merit (FOM) of the CMOS devices falls on the trend line extrapolated from existing industrial CMOS technologies. The impacts of super-halo on V/sub th/ roll-off, DIBL, gate overlap Miller capacitance and junction capacitance in a 50 nm MOSFET are investigated. Strong halo can result in drain-to-halo (body) band-to-band tunneling leakage even at room temperature. Degradation of gate oxide leakage and hot-carrier reliability due to large-angle-tilted halo implant are concerns in 50 nm CMOS transistors.

Moore's Law has set great expectations that the performance of information technology will improve exponentially until at least the end of this decade. Although the physics of silicon transistors alone might allow these expectations to be met, the physics of the long metal wires that cross and connect packages almost certainly will not. Global-level interconnects incorporating large-scale integrated photonics fabricated on the same platform as silicon microelectronics hold the promise of revolutionizing computing by enabling parallel many-core and network switch architectures that combine unprecedented performance and ease of use with affordable power consumption. Over the last decade, remarkable progress has been made in research on low-power silicon photonic devices for interconnect applications, and CMOS-compatible fabrication technologies promise a “Moore's Law for photonics” that could completely change the economics of integrated optics. In this survey, photonic technologies amenable to large-scale CMOS integration are reviewed from the perspective of high-performance interconnects operating over distance scales of 1mm to 100m. An overview of the requirements placed on integrated optical devices by a variety of modern computer applications leads to discussions of active and passive photonic components designed to generate, guide, filter, modulate, and detect light in the telecommunication bands. Critical challenges and prospects for large-scale integration are evaluated with an emphasis on silicon-on-insulator as a platform for photonics.

In this paper, a global feature extraction very large scale integration (VLSI) architecture for real-time object recognition is presented. To minimize the latency between capturing images and final recognition, the image sensor and feature extraction circuits are integrated on the same chip. The digital pixel sensor (DPS) configuration has been used because of its intrinsic compatibility with digital processing circuits. A block-readout architecture developed for DPS has been adopted for the massively parallel processing of image data. As a result, the directional edge filtering at each pixel site for local feature extraction is performed in a line-parallel manner. To eliminate trivial local features, the rank-order filter algorithm has been adapted for the processing and implemented in an efficient global feature extraction circuitry that can retain any given number of relatively more significant features in an image as essential features. This is accomplished in only 11 cycles. A proof-of-concept chip was designed in a 0.18 µm five-metal complementary metal–oxide–semiconductor (CMOS) technology, and the function of this VLSI processor was verified by circuit simulation.