Associative RAM-net memory neural target classifier

The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.

We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτd < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτd < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.

Although sorting networks have extensively been reported in literature (Batcher, 1962), there are a few references that cover a detailed explanation about their VLSI (Very Large Scale of Integration) realization in CMOS (Complementary Metal-Oxide-Semiconductor) technology (Turan et al., 2003). From an algorithmic point of view, a sorting network is defined as a sequence of compare and interchange operations depending only on the number of elements to be sorted. From a hardware perspective, sorting networks can be visualized as combinatorial circuits where a set of denoted compare-swap (CS) circuits can be connected in accordance to a specific network topology (Knuth, 1997). In this chapter, the design of sorting networks in CMOS technology with applicability to VLSI design is approached at block, transistor, and layout levels. Special attention has been placed to show the hierarchical structure observed in sorting schemes where the so called CS circuit constitutes the fundamental standard cell. The CS circuit is characterized through SPICE simulation making a particular emphasis in the silicon area and delay time parameters. In order to illustrate the inclusion of sorting networks into specific applications, like signal processing and nonlinear function evaluation, two already reported examples of integrated circuit designs are provided (Agustin et al., 2011; Jimenez et al., 2011).

Several algorithms are developed to produce optical correla- tion filters for obscured inputs. Each algorithm is optimal for a different set of performance criteria. Computer simulations using binary inputs indicate that some algorithms operate over a wide range of obscurations (down to 5% of the input) while others have restricted operating ranges. © 1998 Society of Photo-Optical Instrumentation Engineers. (S0091-3286(98)01701-2) Subject terms: recognition techniques; pattern recognition; optimal filtering; cor- relation; associative memory.

A transmissive liquid crystal valve for carrying out optical thresholding operations is proposed. It operates in parallel, that is, all the pixels of input are processed together simultaneously. The device is based on an amorphous silicon photoconductor and the features of liquid crystals. It does not require control architecture using very large scale integration (VLSI), so we can achieve a larger aperture ratio, higher resolution (more than 45 lines/mm), and a higher space-bandwidth prod- uct (more than 4310 5 pixels). Its response time is about 10 ms. Its processing capacity can reach approximately 2310 7 thresholding operations/s. The light valve does not break the beam propagation path, and can plug and play easily in optical processing and neural network systems. Its design, fabrication, and thresholding features are presented. © 1996 Society of Photo-Optical Instrumentation Engineers.

In the last forty years the semiconductor industry focused on the downscaling process of the CMOS (Complementary Metal-Oxide-Semiconductor) technology, trying to follow as much as possible the empirical Moore's Law. In the last five years this trend has been facing technology limits that have led to the development of a new research field, named Beyond CMOS, which investigates new electron devices concept and materials that can replace or co-integrate the standard technology, to make large scale integrated (LSI), high performance, low power devices. Carbon nanotubes (CNTs) are considered one of the most promising materials for Beyond CMOS devices, both at front-end and back-end level. The development of the research on this new organic material is due to its nanometer scale dimensions and to its outstanding electrical (metallic and semiconducting behavior, ballistic conduction, current density > 109 A/cm2) and mechanical (Young's modulus ∼1 TPa) properties, nevertheless due to its low mass (mass density ρ = 1300 kg/m3). Among the several CNT applications already reported in literature (interconnections, sensors, transistors, memory, etc.), a particular interest is on their use to build Nano-Electro-Mechanical (NEM) devices, such as resonators and switches. NEM relays based on carbon nanotubes show large-current density drive and high speed operation compared to metal-based NEMS counterparts, low actuation voltage and low power, performances which are promising for radio-frequency (RF) applications, where RF MEM devices are considered as replacement solution for their off-chip and/or solid-state counterparts in front-end transceivers. Most of the previously reported CNT NEM switches concerns relay configuration based on one single movable nanotube and its DC characterization. Despite individual proof-of-concept merits, an electromechanical switch based on a single CNT usually presents an output signal level that is too low for practical applications and a poor reliable fabrication process, which opposes the precise control at wafer level achieved by standard technology. Alternatively, a very large-scale integration of NEM devices requires the exploitation of high-density aligned arrays of nanotubes, grown in precise locations and that could be patterned into well-defined and controlled configurations. The objective of this research work was to develop LSI NEM switches based on high dense carbon nanotube arrays in the back end of the line (BEOL), with conductive and capacitive contacts and tested from DC up to high frequency (RF), in order to evaluate their performances in a wide range of operations. The synthesis process of carbon nanotubes was performed by thermal CVD and temperature, gas concentration and catalyst pretreatment were optimized to achieve high dense aligned CNT arrays. A study on the catalyst geometries and on the substrate materials were performed in order to obtain horizontal aligned arrays grown directly on metallic substrate without density change. We developed a novel surface micromachining process to suspend CNT arrays. The DC characterization of CNT NEM switches was exploited to extract the equivalent electromechanical properties of the CNT membranes, since they behave as a new body material. We extracted an equivalent flexural modulus of 8.5 GPa and a resistivity of 0.0077 Ωcm. The devices, in both configurations, present a very low actuation voltage, below 10 V, lower than typical metal NEM switch for the same dimensions and a comparable switching time. The RF characterization was performed in the telecommunication frequency range (up to 6 GHz) showing reasonably high isolation and low insertion loss. The relay shows a lower reliability than the capacitive switch, due to the elevated drive current which induces the CNTs burning at the metal-to-metal interface. The RF measurements were used to extract the parameters of the proposed devices equivalent lumped model. Several implementations of CNT NEM switches, both for DC (reconfigurable interconnects, logic functions, memories) and RF (signal routing purposes in RF system Front-Ends, phase shifting networks or digitalized capacitor banks) applications, were reported.

A hardware realization of single and two-stage fully parallel associative memories for high speed reliable pattern matching is proposed. We have designed, fabricated and tested the single stage associative memory test chip designed in 0.35 mum two-poly, three-metal CMOS technology which gives very high speed pattern matching performance. But in some applications single stage search or single winner search makes the system less reliable. To increase the reliability of pattern matching system, we have also introduced a cascaded fully parallel associative memory with two-stage winner search. In two-stage pattern matching architecture we have used two different types of associative memories. One is based on the k-nearest-matches search and other one is a special type of associative memory in which winner search is done only among the activated reference patterns. The activation in the second associative memory is done by first associative memory after searching the k-nearest-matches. We have already designed, fabricated and tested the associative memories separately. The complete two-stage pattern matching system is tested here with MATLAB software and hardware realization is currently under the design process.

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Traditional logical equivalence checking (LEC), which plays a major role in the entire chip design process, faces challenges of meeting the requirements demanded by the many emerging technologies that are based on logic models different from the standard complementary metal oxide semiconductor (CMOS). In this article, we propose an LEC framework to be employed in the verification process of superconducting electronics (SCE). Our LEC framework is compatible with the existing CMOS technologies and can also check features and capabilities that are unique to SCE. For instance, the performance of nonresistively biased single-flux quantum (SFQ) circuits benefits from ultradeep pipelining, and verification of such circuits requires new models and algorithms. We, therefore, present the multicycle input dependency circuit model which is a novel model representation of design to explicitly capture the dependency of primary outputs of the circuit on sequences of internal signals and inputs. Embedding the proposed circuit model and several structural checking modules, the process of verification can be independent of the underlying technology and signaling. We benchmark the proposed framework on postsynthesis SFQ and 4-phase adiabatic quantum flux parametron netlists. Results show a comparative verification time of SFQ circuit benchmark, including 16-bit integer divider and ISCAS’85 circuits with respect to the ABC tool for similar CMOS circuits.

An associative memory is a special type of artificial neural network that has the purpose of store input patterns with their corresponding output patterns and efficiently recall a pattern from a noise-distorted version. Presented in this article is a new framework for constructing a binary associative memory model based on two new autoinverse operations called extended XOR/XNOR; these new operations are generated from the XOR/XNOR operations, respectively. Two types of associative memory are generated with this model: the max type (XOR-AM max), which is constructed with the maximum of the extended XOR operation, and the min type (XOR-AM min), which is constructed with the minimum of the extended XNOR operation. The XOR-AM max exhibits tolerance against the presence of patterns distorted by dilative noise, whereas the XOR-AM min exhibits tolerance against the presence of patterns distorted by erosive noise; both types of memory converge in a single step, use the same extended XOR/XNOR operator for learning and recalling phases, operate in heteroassociative and autoassociative modes, and show infinite storage capacity for the autoassociative mode. Finally, computer simulation results are presented for the new memories based on the extended XOR/XNOR (XOR-AM), which have better or equal performance compared to other associative memories. For the experiments with mixed noise, the conditions established by the kernel method proposed by Ritter for Morphological Associative Memories were conserved, and the solution algorithm proposed by Hattori for the construction of the kernel patterns of these memories was modified.

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

Fault identification of analog and mixed signal circuits is very difficult topics for previous few decades. Localization of hard and soft faults in analog circuit is often a troublesome task without a transparent cut methodology. For manufacturing process of Very Large Scale Integration (VLSI) Application Specific Integrated Circuits (ASICs) both fault diagnosis and localization are mandatory. The importance of such analog test has become important due to enhancement of networking and communication sector. This paper gives a brief review on the faults present in analog circuits and different diagnosis methodologies of these faults. Comparison of detection is also demonstrated among some techniques for some of the ITC97 Benchmark circuits.

State-of-the-art technologies cannot be implemented without being expedited by very large-scale integration (VLSI) circuits because computational complexity is continuously increasing. For example, application-specific integrated circuits (ASICs) are required for 5G communications to attain data rates above tens of gigabits per second. Systems for the Internet of Things (IoT) must have extremely efficient hardware to support data transfer within a few milliseconds while operating within a constrained power budget. The digital design gives greater flexibility than the analog design since the digital communication modules are robust and also provide significant immunity to noise and interference. We have a multichannel technology known as orthogonal frequency division multiplexing (OFDM) that combines QAM and FDM (OFDM). To offer several bit streams with a high data rate, 64-QAM or 256-QAM are employed in separate frequency channels with OFDM in 5G. The proposed design, QAM is built utilizing several multiplier architectures, including Vedic multipliers and booth multipliers, and performance evaluation is done concerning area and power using ASIC and CMOS Technology. Aim of the proposed multipliers is that they require significantly fewer components as compared to the naive method. Further complexity reductions are achieved. The obtained result shows that the use of the multiplier module will outperform state-of-the-art modulator efficiency. Using cadence tool 32bit and 64bit QAM design and physical parameters area and power efficiency are estimated and tabulated respectively.

The hallmark of the Rowan College of Engineering undergraduate program is to provide effective laboratory based instruction that illustrates important scientific concepts. This paper presents the results of an effort by the Department of Electrical and Computer Engineering at Rowan University to configure a novel method of teaching the junior level Communications (COMM), Digital Signal Processing (DSP) and Very Large Scale Integration (VLSI) courses under a common laboratory framework. These three courses are taken concurrently during the spring semester of the junior year. Twelve interdisciplinary experiments that cut across individual course boundaries and that integrate hands-on experience and software simulation are proposed. The first four experiments deal with the very basic concepts. The next four experiments expose the students to multimedia standards approved by industry. The last four experiments deal with various applications that link COMM, DSP and VLSI. Software is integrated with the experiments through MATLAB and SIMULINK, C/C++ and Mentor Graphics.

We report a pixel-block scanning-image-segmentation very large scale integration (VLSI) architecture based on a region-growing approach. The input image is divided into pixel blocks in order to process parts of the image in parallel while the pixel status data of the complete image is stored in embedded memory banks. Using the two techniques of (i) limited scan to the boundary of each grown region and (ii) continued block-internal region growing, we have improved the overall segmentation speed and power consumption in comparison to a previous solution. We evaluated the segmentation performance by MATLAB simulation and with a complete application specific integrated circuit (ASIC) design in the case of a one-dimensional scan. Low power dissipation of 44.7 mW and a segmentation performance of 1,000 fps at 8.6 MHz could be achieved. For a two-dimensional scan the block shape and size can be chosen with increased flexibility, and can be optimized to fulfill many different segmentation-speed, power-consumption, and implementation-area requirements. In particular, the pixel-parallel segmentation-unit area can be drastically reduced to 1/10 by changing the pixel-block size from 80 ×2 to 4 ×4 pixels, which still enables real-time segmentation performance.