Transmissive liquid crystal light valve for parallelism optical thresholding operation

Event Abstract Back to Event Logarithmic Hybrid Optical Neural Network-type systems: towards digital-optical cognitive models of robust object recognition Ioannis Kypraios1* 1 Oxford University, Centre for Innovation & Enterprise, APEM Computing Lab, United Kingdom Abstract - By combining the complex logarithmic r-theta mapping of a space-variant imaging sensor [1, 2] with the hybrid digital-optical neural network filter together with a window unit multiple objects of the same class or of different classes can robustly be recognized. The resulted logarithmic r-theta mapping for hybrid digital-optical neural network system or briefly referred to as logarithmic hybrid optical neural network system is shown to exhibit with a single pass over the input data simultaneously in-plane rotation, out-of-plane rotation, scale, log r-θ map translation and shift invariance, and good clutter tolerance by recognizing correctly the different objects within the cluttered scenes. Here, we study the biologically-inspired knowledge learning and knowledge representation [3] achieved by the logarithmic hybrid optical neural network-type of object recognition systems (see Fig. 1 and Fig. 2). We investigate the effects that altering the knowledge representation can have on the problem’s learned knowledge and the problem solving process, in overall. Further, we study the logarithmic unconstrained-, logarithmic constrained-, and logarithmic modified-hybrid optical neural network systems architectures’ designs [4, 5]. We show how the logarithmic unconstrained-hybrid optical neural network object recognition system applies an unconstrained representation of the problem’s knowledge to maximize the search of solutions, how the logarithmic constrained-hybrid optical neural network object recognition system uses a constrained representation of the problem’s knowledge to guide the search towards certain solutions over others in the multidimensional search space, and how the logarithmic modified-hybrid optical neural network object recognition system uses memory-like masks to recall certain solutions over others in the multidimensional search space. Fig. 1. (a) Simplified human retina and visual cortex model used for description purposes only; (b) A digital-optical computational model for the cognitive interaction between the retina and the human visual cortex with the general logarithmic hybrid optical neural network architercture. Fig. 2. Biologically-inspired knowledge learning and knowledge representation with the logarithmic hybrid optical neural network-type of object recognition systems. Figure 1 Figure 2 References [1] C. F. R. Weiman, “Video compression via log-polar mapping”, Real-Time Image Processing II, SPIE Symposium on OE/Aerospace Sensing, Vol. 1295, 266-277 (1990) [2] C. G. Ho et al., “Sensor geometry and sampling methods for space-variant image processing”, Pattern Analysis and Applications, Vol. 5, 369-384 (2002) [3] I. Lee, and B. Portier, "An empirical study of knowledge representation and learning within conceptual spaces for intelligent agents", 6th IEEE/ACIS International Conference Computer and Information Science, 463-468, Melbourne, Australia (2007) [4] I. Kypraios et al., “Fully invariant complex Logarithmic r- map for the Hybrid Optical Neural Network filter for object recognition within cluttered scenes”, 50th Anniversary International Symposium ELMAR 2008, IEEE Region 8/IEEE Croatia Section/EURASIP, Zadar-Croatia, Vol. 1, 141-146 (2008) [5] I. Kypraios et al., “Logarithmic r-θ mapping for hybrid optical neural network filter for object recogntion within cluttered scenes”, Recent Advances in Multimedia Signal Processing and Communications, SCI231, Springer-Verlag Berlin Heidelberg, 91-120 (2009) Keywords: digital-optical, cognitive, object recognition, Robust and Adaptive Systems, Knowledge representation, learning and memory Conference: Neuroinformatics 2013, Stockholm, Sweden, 27 Aug - 29 Aug, 2013. Presentation Type: Poster Topic: Neuromorphic engineering Citation: Kypraios I (2013). Logarithmic Hybrid Optical Neural Network-type systems: towards digital-optical cognitive models of robust object recognition. Front. Neuroinform. Conference Abstract: Neuroinformatics 2013. doi: 10.3389/conf.fninf.2013.09.00066 Copyright: The abstracts in this collection have not been subject to any Frontiers peer review or checks, and are not endorsed by Frontiers. They are made available through the Frontiers publishing platform as a service to conference organizers and presenters. The copyright in the individual abstracts is owned by the author of each abstract or his/her employer unless otherwise stated. Each abstract, as well as the collection of abstracts, are published under a Creative Commons CC-BY 4.0 (attribution) licence (https://creativecommons.org/licenses/by/4.0/) and may thus be reproduced, translated, adapted and be the subject of derivative works provided the authors and Frontiers are attributed. For Frontiers’ terms and conditions please see https://www.frontiersin.org/legal/terms-and-conditions. Received: 09 Apr 2013; Published Online: 11 Jul 2013. * Correspondence: Dr. Ioannis Kypraios, Oxford University, Centre for Innovation & Enterprise, APEM Computing Lab, Begbroke, Oxfordshire, OX5 1PF, United Kingdom, ioanniskyp@yahoo.com Login Required This action requires you to be registered with Frontiers and logged in. To register or login click here. Abstract Info Abstract The Authors in Frontiers Ioannis Kypraios Google Ioannis Kypraios Google Scholar Ioannis Kypraios PubMed Ioannis Kypraios Related Article in Frontiers Google Scholar PubMed Abstract Close Back to top Javascript is disabled. Please enable Javascript in your browser settings in order to see all the content on this page.

We propose a broad-based target classifier that recognizes a target on the principle of pattern matching based on associative memory, and can be implemented in hardware with standard complementary metal-oxide semiconductor (CMOS) cells. A major drawback in the field of neural networks is the inability to implement network designs in hard- ware inexpensively. Here we have designed an associative RAM-net memory neural classifier, which is based on the associative memory model of a winner-take-all classifier. In this model extensive use of ordi- nary random access memory is made. The benefit of this approach is that the entire architecture can be designed with current CMOS standard cells application-specific integrated circuit (ASIC) technologies as op- posed to current analog very large scale integration (VLSI) approaches. Since RAM can be easily added using the standard cell ASIC approach, a low-cost implementation for a wide variety of neural classification prob- lems is provided. The integration of all necessary features on a single chip results in an easily implementable, low-chip-count classification sys- tem. A full gate-level design of the architecture is created and simulated using the VHDL hardware programming language (Navabi, 1993; Mentor Graphics, 1992). The results are very encouraging, and warrant further research into various memory types and configurations. © 1998 Society of Photo-Optical Instrumentation Engineers. (S0091-3286(98)00507-8) Subject terms: target classifier; neural networks; associative memory; RAM-net memory.

Automobile machine vision is a potential application for hardware neural networks. This paper suggests a future system concept which combines front-end low-level processing in smart pixels and a massively interconnected optical neural network. Two smart pixels devices fabricated in Ferroelectric Liquid Crystal on Silicon technology will be described. The first device implements an array of somas, while the second device implements an array of synapses. These are effectively generic building blocks for scalable neural network architectures. Experiments have demonstrated actions of optoelectronic neurons formed by the smart pixels. An optical neural network system has been investigated in a simulation of an autoassociative memory for road sign recognition.

: This report describes techniques for very large scale integration (VLSI) implementation of arithmetic algorithms. The report describes an algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root. Keywords include: Very large scale integration (VLSI); and Floating point chip design.

The neural network system with terminal attractors is pro- posed for pattern recognition. By the introduction of the terminal attrac- tors, the spurious states of the energy function in the Hopfield neural networks can be avoided and a unique solution with global minimum is obtained. The computer simulations show the usefulness of the method for pattern recognition. Based on the terminal attractor neural network, we proposed the optical neural network with the terminal attractor model. The results show that the recognition rate is considerably enhanced by the introduction of the terminal attractors. © 1996 Society of Photo-Optical Instrumentation Engineers.

Although sorting networks have extensively been reported in literature (Batcher, 1962), there are a few references that cover a detailed explanation about their VLSI (Very Large Scale of Integration) realization in CMOS (Complementary Metal-Oxide-Semiconductor) technology (Turan et al., 2003). From an algorithmic point of view, a sorting network is defined as a sequence of compare and interchange operations depending only on the number of elements to be sorted. From a hardware perspective, sorting networks can be visualized as combinatorial circuits where a set of denoted compare-swap (CS) circuits can be connected in accordance to a specific network topology (Knuth, 1997). In this chapter, the design of sorting networks in CMOS technology with applicability to VLSI design is approached at block, transistor, and layout levels. Special attention has been placed to show the hierarchical structure observed in sorting schemes where the so called CS circuit constitutes the fundamental standard cell. The CS circuit is characterized through SPICE simulation making a particular emphasis in the silicon area and delay time parameters. In order to illustrate the inclusion of sorting networks into specific applications, like signal processing and nonlinear function evaluation, two already reported examples of integrated circuit designs are provided (Agustin et al., 2011; Jimenez et al., 2011).

Process quality and delivery time have received increasing attention in the highly competitive electronics industry. Many studies have proposed process capability indices (PCIs) to assess process effectiveness. However, methods to assess the performance in terms of processing and delivery times of products have seldom been discussed. The conventional PCIs can no longer assess the processing time (PT) and delivery time (DT) performance objectively or identify the relationship between PCIs and the non-conformance rate of PT or the conformance rate of DT. Lacking an effective performance index or an objective testing procedure to assess process/product performance will lead to inefficiency or a high manufacturing management overhead cost. Therefore, this study offers effective performance indices (i.e., PCIs) to assess the PT and DT performance for very large scale integration (VLSI). The uniformly minimum variance unbiased (UMVU) estimators of the proposed PCIs are derived under the assumption of a normal process distribution. The PCI estimators are then employed to construct a one-to-one relationship between the PCIs and the conformance rate of DT or non-conformance rate of PT, respectively. Finally, hypothesis testing procedures for the proposed PCIs are also developed. The testing procedure can be used to determine whether DT or PT can satisfy a customer’s requirements.

The construction of computer systems containing integrated circuit logic components with very large scale integration (VLSI), that is, many thousands of gates, is inevitable. Such levels of integration have already been achieved in memory components. There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.

Very large scale Integration (VLSI) was used to create hardware which initiates by the explanation of algorithm as well as employs computer program. In digital systems, multiplier and adder are the fundamental components in design of integrated circuit applications. High speed devices play an essential role in VLSI applications. Adder enhancement is used in miscellaneous application in new VLSI system like multiplier design, ALU and etc. An efficient adder circuit design is used to optimize various metrics. But, design complexity was not reduced by existing VLSI design. To handle such limitations, Deep Fully Connectedness Convolutional Broken Stick Regressive Brent-Kung Adder Enhancement (DFCCBSRBKAE) Technique is introduced in VLSI circuits. Input layer, two hidden layers as well as output layer comprises four layer of DFCCBSRBKAE Technique. The carry inputs are transferred to input layer. Input data is transferred to hidden layer 1. Broken-stick regression analysis is performed for pre-processing data. Next, pre-processed data is transferred to hidden layer 2. Carry generation and post-processing is carried out in hidden layer 2 and the output results are covered by the convolution. At last, outcomes were attained within output layer. This in turn helps to perform an efficient adder enhancement of digital multiplier with minimal power and time consumption. The performance of DFCCBSRBKAE Technique is determined by power and time consumption. DFCCBSRBKAE Technique reduces the area, speed, and delay and power consumption of adder enhancement compared with conventional methods.

In this paper, a new version of very large scale integration (VLSI) layouts compaction problem is considered. Bar visibility graph (BVG) is a simple geometric model for VLSI chip design and layout problems. In all previous works, vertical bars or other chip components in the plane model gates, as well as edges, are modeled by horizontal visibilities between bars. In this study, for a given set of vertical bars, the edges can be modeled with orthogonal paths known as staircases. Therefore, we consider a new version of bar visibility graphs (BsVG). We then present an algorithm to solve the s-visibility problem of vertical segments, which can be implemented on a VLSI chip. Our algorithm determines all the pairs of segments that are s-visible from each other.

The fast-moving telecommunications industry is driving the demand for Very Large Scale Integration (VLSI) design approaches that can achieve higher performance at lower power consumption and higher reliability. This paper presents enhanced VLSI design methodologies tailored for telecommunications systems, with an emphasis on key performance metrics optimization, such as speed, power efficiency, and scalability. The new strategies presented incorporate novel design paradigms including power-aware architectures, adaptive clocking mechanisms, and high-density integration techniques. Additionally, deep sub-micron technology has brought with it a whole new set of challenges, such as increased leakage currents and signal integrity problems, which are mitigated through novel circuit-level techniques and layout optimizations. One of the major focuses in the research is hardware integration, especially the accelerators needed for specialized functions in telecommunications: signal processing and encryption. Next, design methodologies supported by innovative CAD tools and simulation environments have been discussed; this helps increase design efficiency as well as helps reduce time-to-market. To that end, low-power techniques such as multi-threshold voltage and power gating have been focused on in relation to the design of energy-efficient hardware for telecommunications. This paper demonstrates, through simulation results and case studies, that the proposed VLSI strategies can improve system performance significantly while maintaining power efficiency and low cost. The findings contribute to the ongoing research and development in VLSI technology and offer a roadmap for designing next-generation telecommunications systems capable of supporting emerging applications such as 5G, IoT, and beyond. These strategies not only enhance the robustness of the design but also open the way toward more scalable and adaptive telecommunications infrastructures

The advantage of optical signal processing and computing is mainly due to its two-dimensional complex computing ability with the fastest speed. Of computation algorithms, quite a few are iterative or recursive, such as vector or matrix multiplication over a given matrix for many times, and the computation of derivatives of much high order, etc. These algorithms are also suitable for optical computing . To perform iterative algorithms, the output from a computation step reenters the system as the input for the next step, therefore a feedback loop is needed. Many optical signal processing systems have spatial light modulators that are electrically addressed, and the photon-to-electron and electron-to-photon conversions reduce the processing speed and increase the system complexity. In this paper we propose an all-optical signal processing system for performing the iterative algorithms by using a four wave mixing material which introduces a feedback loop in the system. We believe that this system may also be used as an optical two-dimensional dynamic memory device.

Recent advances in electro-optics have brought into use communication and information theory to analyze performance in coherent and incoherent optical information processing systems. An optical information processsing system can be analyzed with many of the same concepts of linear system theory (e.g., spatial impulse response, spatial frequency and spatial domain synthesis, etc.), and the photographic images to be processed can be regarded in the same manner as time signals (e.g., spatial frequency content, spatial amplitude and phase modulation, space-bandwidth product, etc.). Both coherent and incoherent optical processing systems can be treated as linear systems, and the processing operation can generally be carried out by communication theory concepts. Although coherent optical information processing operations have been used for performing complex amplitude operations, complex processing can also be performed with incoherent or white-light illumination. The importance of optical information processing operations, either coherent or incoherent, is due to the basic Fourier transform properties of lenses. In this paper, we will discuss mostly the incoherent systems because they are of more recent interest and possess certain advantages, we feel, over the traditional coherent optical processors. Experimental illustrations of the results are provided. In view of the broad area in optical processing of photographic images, we will confine ourselves to a few applications that we consider of general interest. We apologize for the omission of other techniques and applications, and for neglecting the inclusion of their references.

As the demand for artificial intelligence continues to grow, there is a need for specialized hardware that can efficiently process and power AI algorithms. This is where VLSI (Very Large-Scale Integration) design comes into play. By integrating millions, or even billions, of transistors onto a single chip, VLSI design enables the creation of powerful AI-integrated circuits. However, designing hardware specifically for artificial intelligence poses its own set of challenges. The complexity of AI algorithms and the need for parallel processing capabilities demand innovative solutions. VLSI designers must carefully consider factors such as power consumption, heat dissipation, and the integration of specialized neural network accelerators. In addition to these considerations, VLSI designers must also address the scaling limitations of semiconductor technology. As AI algorithms become more complex, the demand for advanced VLSI architecture increases. Designers must find ways to enhance transistor density and performance while overcoming the limitations imposed by the physical laws governing semiconductor manufacturing. In-Memory Computing (IMC) is an emerging paradigm designed to overcome the limitations of the traditional Von Neumann architecture, particularly for energy-efficient AI applications. Traditional computing systems suffer from the "memory wall"—a bottleneck caused by the constant transfer of data between the CPU and memory. This leads to inefficiencies in latency, bandwidth, and energy consumption, especially for AI tasks which involve huge volumes of matrix operations and data movement. Keywords: Very Large-Scale Integration (VLSI), Artificial Intelligence (AI), In-memory computing (IMC), Neuromorphic, multiply-and-accumulate (MAC), RRAM (Resistive RAM), MRAM (Magnetoresistive RAM), PCM (Phase-Change Memory), FeFET (Ferroelectric FET), spiking neural networks (SNNs)

We focus on the evaluation of the applicability of the classical and well-established linear polarimeter to the measurement of linear retardance in the presence of phase flicker. This analysis shows that there are large errors in the results provided by the linear polarimeter when measuring the linear retardance of a device. These errors depend on the specific retardance value under measurement. We show that there are some points where this limitation can be used to measure the fluctuation amplitude consistently. An elegant method is further proposed, enabling the measurement of the average retardance value, thus extending the applicability of the classical linear polarimeter. Experimental characterization results are provided for various electrical sequences addressed onto a parallel aligned liquid crystal on silicon (LCoS) display. Good agreement is obtained with experiment, thus validating the linear polarimeter methodology proposed. Furthermore, results are provided for the LCoS in two reflection geometries, perpendicular incidence with and without nonpolarizing beam splitter, demonstrating robustness of the method. As a result, the evaluation of both phase modulation range and flicker magnitude for any electrical sequence addressed can be easily obtained, which is very important for optimal use of LCoS displays in applications.