High performance fully-depleted tri-gate CMOS transistors

As Si Metal Oxide Semiconducting Field Effect Transistors (MOSFETs) have continued to scale Short Channel Effects (SCE) have become exacerbated by the inability to continue scaling the Equivalent Oxide Thickness (EOT) of the device significantly beyond what was realized with the introduction of High K Metal Gate (HKMG) MOSFETs at the 45nm technology node. Since EOT scaling has not kept pace with the gate length (Lg) scaling needed to continually increase the transistor drive current, device makers have instead elected to introduce FinFET and Tri-Gate transistors with inherently better electrostatic control in order to realize reasonable SCE in the device. High mobility channel materials, such as Ge, are attracting increasing interest due to the possibility of realizing increased performance even without scaling the Lg of the device (1). Ge is particularly attractive for use as a channel material for P-type MOSFETs (PMOSFETs) due to its high hole mobility and Si processing compatibility. In fact, we have demonstrated experimental PMOSFET devices with hole mobilities significantly higher than what can be obtained on Si, Fig. 1. However, a significant remaining challenge to incorporating Ge into VLSI production is obtaining a stable and well-passivated dielectric/semiconductor interface using tooling and substrates compatible with current 300mm Si VLSI High Volume Manufacturing (HVM) in order to achieve reasonable device performance at sub 1nm EOTs (2). In this paper we will report progress on surface passivation and functionalization of Ge channel surfaces, as well as High K dielectric layer growth by Atomic Layer Deposition (ALD) and the resulting electrical properties measured by fabricated MOSFETs and Metal Oxide Semiconducting Capacitors (MOSCAPs). The Ge channel devices were formed on 300 mm Si wafers using Ge grown by an epitaxial process including a graded SiGe buffer layer. We have utilized a TEL CertasTMChemical Oxide Removal (COR) process (3), which uses dry HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. We have also studied Ge oxide interface layer formation by plasma oxidation using a Slot Plane Array (SPA) antenna (4) utilizing in-line X-ray Photoelectron Spectroscopy (XPS) to measure Ge and high K oxide thickness on monitor wafers fashioned by the same Ge epitaxial process used to make the electrical devices and compared it to the equivalent Si oxidation process, Fig. 2. Various other passivation and interface schemes were investigated and will be discussed, contrasted and compared including ozone oxidation, Al oxide passivation/interface layers, SPA plasma nitridation, and thin amorphous Si passivation layers. We have utilized Hf oxide grown by a previously reported ALD process (5) as the High K dielectric for our devices, and TiN as the metal gate. Our results show that Ge channel devices can be fabricated on 300mm Si substrates using Si VLSI-compatible toolsets and infrastructure and resulting in reasonable device characteristics, Fig. 3. Thus, Ge channel MOSFETs are found to be a promising technology for use in HVM at future VLSI technology nodes.

Advanced, fully depleted devices such as FinFET or Tri-Gate transistors are increasingly sought after to enable density and gate length (L g ) scaling in future technology nodes. As gate-pitch scaling continues, the fin pitch must also be reduced to maintain proper electrostatics control in short L g devices. However, in the absence of proper junction engineering, further scaling of L g below 10nm would compromise off-state leakage (I off ) due to degraded drain-induced barrier lowering (DIBL) and subthreshold slope (SS) as a result of poor short channel control. This may be mitigated by scaling the gate dielectric thickness to maintain good control of short-channel effects (SCE), but it leads to an exponentially increasing gate leakage current and power consumption. Increasing channel doping could be an alternative to improve SCE, but it decreases carrier mobility due to impurity scattering and gives rise to random dopant fluctuations (RDF) issue. Additionally, decreasing the fin pitch to preserve short channel integrity reduces the source/drain (S/D) contact area which leads to an increase in external parasitic resistance (R ext ) that has become a critical technology barrier to achieving ITRS's performance target in advanced nodes.

At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process. Fabricated on a bulk silicon substrate, these transistors feature a third-generation high-k + metal-gate technology and a fifth generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70 mV/decade) and very low DIBL (∼50 mV/V) values that are critical for low voltage operation. Self-aligned contacts are implemented along with the tri-gate transistors to eliminate restrictive contact-to-gate registration requirements from scaling the gate pitch. This enables an SRAM cell size of 0.092 μm2. High yield and reliability have been demonstrated on multiple microprocessors.

CMOS transistors with a 50 nm physical gate length are demonstrated. Super-halo, implemented by angle-tilted implantation, is utilized to control V/sub th/ roll-off down to a gate length of 40 nm. Super-halo also provides V/sub th/ adjustment as well as a retrograde channel to suppress subsurface body punch-through. 935 /spl mu/A//spl mu/m and 395 /spl mu/A//spl mu/m on-state drive currents were achieved for n- and p-channel MOSFETs, respectively, with a V/sub dd/ of 1.5 V. The I/sub drive//(C/sub ox(inv)/V/sub dd/) figure-of-merit (FOM) of the CMOS devices falls on the trend line extrapolated from existing industrial CMOS technologies. The impacts of super-halo on V/sub th/ roll-off, DIBL, gate overlap Miller capacitance and junction capacitance in a 50 nm MOSFET are investigated. Strong halo can result in drain-to-halo (body) band-to-band tunneling leakage even at room temperature. Degradation of gate oxide leakage and hot-carrier reliability due to large-angle-tilted halo implant are concerns in 50 nm CMOS transistors.

Over the last technology nodes, the continuous reduction of the CMOS dimensions has been pushing the physical limits of the transistor into numerous ends. Consequently, a straightforward linear scaling of device dimensions does not apply anymore to all the aspects of the CMOS transistor. For instance, the aggressive scaling of the transistor gate pitch requires that both the gate length and the S/D contact dimensions are reduced in size; constraining the gate, the sidewall spacers and the S/D contacts to compete continuously for space. On the other hand, the transistor gate length has also to follow a different scaling law and is kept as large as possible to ensure a proper electrostatic control. A direct consequence of this approach is the need to keep on decreasing the S/D contact resistance, which currently constitutes a new bottleneck in the scaling of modern CMOS. Aside from being able to reduce the physical dimensions of the contact, it is paramount to minimize the metal/semiconductor intrinsic resistivity which has now become a major roadblock to be conquered. Recently, the cumulated efforts of the scientific and engineering communities have substantially extended the physical limits of the S/D contact resistance thanks to the increase in the concentration of activated dopants in the semiconductors and to the engineering of their Schottky barrier. The latter is achieved by integrating metals with a weak Fermi level pinning at the interface with the semiconductor. As a result, contact resistivities as low as 2x10-9 Ω.cm2 [1] and 8.4x10-10 Ω.cm2 [2] have been reported for n-Si-TiSi(amorphous) and p-Si30Ge70-TiSi(amorphous) with dopant concentrations as high as 6x1020cm-3 and 1x1021cm-3[1,2]. Although these accomplishments are very impressive, little is known on the intrinsic limits that will ultimately determine the contact resistivity and it remains unclear whether even higher doping concentrations would be desirable or not. In this contribution, we will report a fundamental study of the factors that set the contact resistivity between metals and highly doped semiconductors. We will investigate the case of n-type doped Si contacted with amorphous TiSi combining first-principles calculations with Non-Equilibrium Green functions transport simulations [4][5]. We will show that, whereas the metal/semiconductor intrinsic contact resistivity initially scales with the doping concentration, it is found to saturate at ~2x10-10 Wcm2, as of a doping concentration of ~5x1021 cm-3. From this concentration on, electron injection is governed by Ohm’s law. It turns out that, in such high doping regimes, the electron injection does no longer depend on the barrier height set by the interface potential to be crossed. In turn, it becomes less sensitive to the chemical composition of the interface/degree of disorder and is limited by the intrinsic transmission probability of electrons being injected from the metal into the semiconductor. The latter depends on both the effective masses of the metal and of the semiconductor [3] and imposes an intrinsic physical limit to the contact resistance. We will show that, in this regime, contacting metals with a heavy electron effective mass are favorable to increase the transmission probability and, hence, to reduce of the semiconductor-metal intrinsic contact resistivity. Acknowledgements: The authors thank the imec industrial affiliation core CMOS program and quantumwise for financial and technical supports, respectively.

In CMOS technology, as we decrease the gate length of MOSFET from µm to nm, its performance is effected due to increased short-channel effect (SCE) and leakage current (Xie et al. in IEEE Trans Electron Devices 59, 2012 [1]; Loan, Quresh, and Sundar Kumar Iyer in IEEE Trans Electron Devices 5, 2010 [2]). Multigate transistors like double gate, tri-gate transistors, FinFETs are proposed to reduce SCEs which finally result in improvement of current flowing through device (Agostinelli et al. in IEEE Trans Very Large Scale Integr (VLSI) Syst 5, 2010 [3]; Singha et al. in Optimization of Underlap Length for DGMOSFET and FinFET, 2015 [4]; Sahu et al. in J Microelectron, Electr Compon Mater 44(2), 2015 [5]). Buried oxide layer is introduced in the substrate of FinFET to decrease parasitic capacitance which is formed between source/drain region and substrate of FinFET (Sun et al. in IEEE Trans Electron Devices 58, 2011 [6]; Ponton in IEEE Trans Circuits Syst 56(5), 2009 [7]). Thus, the paper highlights the effect of variation in buried oxide layer thickness of SOI FinFET on electrical parameters like threshold voltage, drain-induced barrier lowering (DIBL), on current, off current, on/off current ratio. Various simulation results are shown in the research paper using TCAD software.

Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering

In this paper, a behavioral model of threshold voltage for normally-off (enhancement mode) AlGaN/GaN based tri-gate HEMT is proposed. AlGaN/GaN based tri-gate HEMT devices have additional sidewall gates and show threshold voltage variation with decreasing device width. The proposed model captures strain relaxation with reduction in device width, which is one of the primary reason for change in V th in AlGaN/GaN tri-gate devices. Model shows excellent agreement with state-of-the-art experimental and simulation data.

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.

A capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) fully depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented and retention time compatible to eDRAM requirements is measured at 85/spl deg/C. Nondestructive reading is demonstrated at 25/spl deg/C and disturb margins are deeply investigated, showing the possibility of matrix integration. This study is then extended to another type of FD device: the very promising double gate architecture.

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

Technical and economic factors have caused the field of physical design automation to receive increasing attention and commercialization. The steady down-scaling of complementary metal oxide semiconductor (CMOS) device dimensions has been the main stimulus to the growth of microelectronics and computer-aided very large scale integration (VLSI) design. The more an Integrated Circuit (IC) is scaled, the higher its packing density becomes. For example, in 2006 Intel's 65-nm process technology for high performance microprocessor has a reduced gate length of 35 nanometers. In their 70-Mbit SRAM chip, there are up to 0.5 billion transistors in a 110 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip size with 3.4 GHz clock speed. New technology generations come out every two years and provide an approximate 0.7 times transistor size reduction as predicted by Moore's Law. For the ultimate scaled MOSFET beyond 2015 or so, the transistor gate length is projected to be 10 nm and below. The continually increasing size of chips, measured in either area or number of transistors, and the wasted investment involving fabricating and testing faulty circuits, make layout analysis an important part of physical design automation. Layout-versus-schematic (LVS) is one of three kinds of layout analysis tools. Subcircuit extraction is the key problem to be solved in LVS. In LVS, two factors are important. One is run time, the other is identification correctness. This has created a need for computational intelligence. Fuzzy attributed graph is not only widely used in the fields of image understanding and pattern recognition, it is also useful to the fuzzy graph matching problem. Since the subcircuit extraction problem is a special case of a general-interest problem known as subgraph isomorphism, fuzzy attributed graphs are first effectively applied to the subgraph isomorphism problem. Then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the subcircuit extraction problem. Similarity measurement makes a significant contribution to evaluate the equivalence of two circuit graphs. To evaluate its performance, we compare fuzzy attributed graph approach with the commercial software called SubGemini, and two of the fastest approaches called DECIDE and SubHDP. We are able to achieve up to 12 times faster performance than alternatives, without loss of accuracy

Nowadays, process-induced stress is the preferential industrial method to enhance circuit performances. One of the most popular techniques is the strain induced by contact etch-stop layer. This technology induces a drain-current enhancement which depends on the device dimensions. This strong behavior has already been reported in the literature. In this paper, we propose a simple semianalytical physical model to understand the origin of this dependence and to highlight the physical limitations of the stress techniques. With this model, after a calibration, it would be possible to predict the MOSFET performance for a given transistor gate length. This approach is validated by experimental data and explains the reduction of the drain-current enhancement that is observed for ultrasmall gate-length MOSFET.

Motorola's Graded Channel CMOS (GCMOS) provides a low cost and highly integrated solution for mixed-mode and RF applications. The GCMOS transistor has demonstrated performance advantages over standard CMOS processes with the same physical gate length. The graded channel, fabricated using lateral diffusion, provides a deep submicron Leff even with a gate length of 0.6 micrometer. The technology is constructed using a process that is fully compatible with standard CMOS manufacturing. However, in order to assure adequate threshold control, the lateral diffusions must be well-behaved. This means that both the channel implant and the source/drain implant must be truly self-aligned, requiring good control of the implants as well as the gate electrode profile. For aggressively designed GCMOS devices, small deviations of the implant beam from normal incidence can lead to unacceptable shifts in threshold. The sources of such error, and current industry standard machine tolerances for each, are discussed. Strategies for ensuring adequate control include a regimen of in-line process monitors, approximate error cancellation of the channel and source/drain implants, and the use of quadrature implants. By using these strategies a manufacturable process has been achieved.

Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced x-ray emission spectrometry (LEXES) and other conventional techniques such as Four Point Probe (FPP) and secondary ion mass spectrometry (SIMS), we quantified SDE dopant loss during the CMOS process and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively. Novel junction structures with electrostatic channel extension (ESCE) MOSFET for sub-20 nm gate-length transistor are presented as well.