3-D ICs: Motivation, performance analysis, technology and applications

VLSI computing is critical in chip fabrication in today's digital age. Moore's law demands that "the number of transistors on a microchip doubles every two years" in addition to that "the count of transistors employed in a chip size is reduced". As a result, this rule is dictating the electronics industry by reducing chip area, size, and power consumption while simultaneously enhancing chip fabrication strength. The arithmetic circuits are constructed in this work, by boosting the efficiency of circuits by considering die space as a constraint. Overall, arithmetic circuits have a bunch of usages in processing architecture. The XOR gate and multiplexer are utilized in this study to make compressor circuits more efficient by taking into account area, power, and delay. To examine the arithmetic circuit's performance, the load capacitance is customized and the power dissipation across the capacitor is studied.

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and

Boron nitride (BN) multi-layers are proposed as dielectric material for both horizontal and vertical graphene nanoribbon interconnects. The layer number dependence of the out-of-plane dielectric constant of BN multi-layers is utilized to simultaneously reduce the interlayer dielectric thickness and the crosstalk delay at 7 nm CMOS technology node. Since crosstalk effects are manifested more strongly in denser interconnects, the proposed all-two-dimensional-materials-based interconnection schemes are compared with Cu/low-k technology in terms of crosstalk delay. Results show that by reducing the interlayer dielectric thickness from 20 nm to 2 nm, the crosstalk delay ratio of the horizontal and vertical graphene nanoribbon interconnects to the Cu/pSiCOH counterparts decreases by 27.06% and 12.86%, respectively. It is also shown that as the interconnect length increases, both horizontal and vertical graphene nanoribbon interconnects with the BN dielectric prove more advantageous than the Cu/low-k counterparts.

Design and analysis of a low-swing driver scheme for long interconnects

The fabrication technology for Si-MEMS devices is mainly derived from the processes used for the realization of microelectronic devices. However, due to the specific demands for MEMS, there are special processes needed for MEMS devices. In this chapter, after reviewing general aspects of microtechnology some of the specific MEMS- processes will be discussed, e.g. bulk-micromachining, surface micromachining, DRIE and SOI-technology. The success of microelectronic is strongly related to fabrication aspects. Using advanced lithography processes and sophisticated physical and chemical methods for pattern transfer minimum feature size well below 0.25 µm is achieved in today's large scale production. The reduction of minimum feature size has improved the performance of the microelectronic devices (power consumption, driving voltage, delay time) and has increased the possible complexity (transistors per chip) while keeping costs per chip almost constant during the last decades. This is achieved by a "giant in one time concept" based on parallel pattern definition processes (e.g. billions of structures are defined with one lithography step) and batch processing of several wafers at one time (e.g. oxidation). Si-based MEMS, or more generally speaking, Si-based microsystems technology, is benefitting from the achievements in microtechnology. However, it is worth while keeping in mind also the differences between microelectronics and microsystems. First, the demands on miniaturization for microsystems are not as strong as for microelectronic devices. Especially in micromechanical devices (e.g. sensors) minimum feature sizes are often well above one micrometer. Even in monolithically integrated microsystems the corresponding microelectronic part does not demand for sub-micrometer features in most cases. Secondly, the degree of standardization and the

We report the thermal chemical vapor deposition of vertically-aligned multiwalled carbon nanotube forests directly onto electrically conductive cobalt disilicide (CoSi2) support using Fe as catalyst. We find that CoSi2 support layer is able to prevent the agglomeration of the catalyst and favor vertically-aligned growth better than a SiO2 support and comparable to an Al2O3 support. This is an unusual behavior for a conductive support. This is because CoSi2 has a lower surface energy than most metals or metallic compounds. This has great benefits in the application of CoSi2 as support for CNTs as horizontal and vertical interconnects.

Due to their flexibility and compatibility with silicon devices, the use of carbon nanotubes as scaffolds for metal interconnect in flexible and wearable electronics has been proposed. This paper examines the performance of dual-height carbon nanotubes as flexible scaffolds for horizontal and vertical interconnects. For this purpose, a number of test structures have been designed and fabricated and their electrical and mechanical performance been investigated.

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. There are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB (embedded Wafer Level BGA) is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. Furthermore, 3D eWLB technology enables 3D IC and 3D SiP packaging with vertical interconnection. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. This paper will highlight some of the recent advancements in 3D eWLB packaging and integration as well as what is being envisioned and developed to address future technology requirements in 3D packaging. The advantage of 3D eWLB technology and applications of 3D packaging will be presented with several examples. The process flow of 3D eWLB fabrication, assembly and packaging challenges, and performance characteristics will be also discussed.

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. There are some restrictions in possible applications for Fan-In WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB (embedded Wafer Level BGA) is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. Furthermore, 3D eWLB technology enables 3D IC and 3D SiP packaging with vertical interconnection. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. In this paper, there will be discussion of the recent advancements in 3D eWLB packaging and integration as well as what is being envisioned and developed to address future technology requirements in 3D packaging and 3D SIP. The advantage of 3D eWLB technology and applications of 3D packaging will be presented with several examples. The process flow of 3D eWLB fabrication, assembly and packaging challenges, and performance characteristics will be also discussed.

With the advancement of technologies, interconnect circuits are shrinking dramatically. Capacitances of interconnects are increasing due to minimized wire size and inter wire spacing. As a result, interconnect power consumption, delay, and crosstalk are increasing significantly, which is affecting overall interconnect performance. Various techniques such as buffer insertion, shielding, skewing, and encoding are used to minimize delay, crosstalk, and power consumption. This paper studies a set of encoding methods for reducing power consumption, crosstalk, and delay, and also presents a comprehensive comparison and analysis of these encoding techniques.

Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption. Design/methodology/approach – The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain minimum or no crosstalk effects. The proposed encoding method uses the bus invert (BI) method. The proposed encoding methods are able to avoid the worst-case crosstalks while consuming lesser power during transmission in VLSI interconnects. Findings – It is observed that the proposed encoders reduced/eliminated the worst-case crosstalk by reducing SSN. The encoding method I also reduces Type 0 crosstalk by 100 per cent, while Type 1 crosstalk is reduced by 36.4 per cent and Type 2 is reduced by 16.8 per cent. The average simultaneous switching is reduced by 51.1 per cent. Similarly, encoding method II reduces switching activity by 10.3 per cent, whereas the coupling activity is reduced by 35.4 per cent. Furthermore, encoding method II also reduced Type 0, Type 1 and Type 2 crosstalk by 100, 36.9 and 27.1 per cent, respectively. Hence, the proposed encoding methods reduced the worst-case crosstalk completely. Research limitations/implications – In VLSI technology, the reduction in feature size and the increase in operating frequency are quite rapid. This leads to higher propagation delay, crosstalk and power dissipation through the interconnects. Most of the previously proposed encoders/decoders have turned out to be unsuitable for RLC modelled interconnects. Hence, the proposed encoder would be extremely useful for crosstalk reduction in newer operating conditions. Practical implications – The encoding method I identifies the harsh crosstalks, that is Type 0 and Type 1, in the inverted and non-inverted forms of incoming data with respect to the previous data. The data having minimum crosstalk in the inverted and non-inverted forms are only sent through the transmission line. The encoding method I also removes the worst-case crosstalk and simultaneously reduces other mild crosstalks. The removal of worst-case crosstalk improves the overall performance of the interconnect. The encoding method II identifies Type 2 crosstalk along with Type 0 and Type 1 similar to encoding method I. Furthermore, the encoding method II exhibits an improvement over method I in terms of reduction in crosstalk and power dissipation. Originality/value – This paper proposes a novel encoding method to reduce worst-case crosstalk effects that reduces SSN. The proposed encoding methods achieve their purpose of crosstalk reduction for several technology nodes.

A novel via hole metallization method is presented, where the vias are drilled in polyimide/copper (PI/Cu) flexible printed circuit boards (PCBs) using KrF excimer pulses, and then pre-metallized using a scanned Ar+ laser. In the premetallization step, a thin (20–50 nm) and narrow (2–10 μm) palladium layer is deposited on the polyimide-covered side of the PCB and on the wall of the vias using the laser-induced chemical liquid-phase deposition method. After the pretreatment, the Pd covered holes are immersed into a Cu electroless plating bath. Plated copper vertical and horizontal interconnects are analyzed by optical microscopy, focused ion beam, profilometry and resistivity measurements. The results show that the copper deposits formed on the pre-metallized surface of PCBs have high chemical purity, excellent adhesion and almost bulk conductivity, but, so far, due to unclear reasons, high through hole resistance.

The article presents a comprehensive study of the legal relations between the prosecutor, the investigator, and operational units during the pre-trial investigation of war crimes under the conditions of martial law. It reveals their legal nature, content, structure, and functional purpose within the system of criminal procedure. It is substantiated that these legal relations form an integral system of authority-procedural connections combining the prosecutor’s managerial, coordination, and supervisory functions with the investigator’s professional autonomy and the operational independence of specialized units. Theoretical and practical foundations of prosecutorial supervision in war crimes proceedings are determined, the distinction between prosecutorial supervision and departmental control is outlined, and the vertical and horizontal interconnections between the subjects of proof are characterized. The study analyzes current Ukrainian legislation, international standards for investigating war crimes, and the practice of their implementation in the interaction among the prosecutor’s office, pre-trial investigation bodies, and operational structures. It demonstrates that the effectiveness of documenting and proving war crimes largely depends on proper coordination of actions, the unity of evidence policy, and ensuring the legality of using results of operational-search and covert investigative (search) actions. The paper highlights problems of law enforcement associated with the uncertainty of the limits of prosecutorial supervision, conflicts between national norms and international standards of admissibility of evidence, as well as the absence of unified procedures for interagency cooperation. The article proposes directions for improving Ukraine’s criminal procedural legislation, which include clear normative delineation of powers among the prosecutor, investigator, and operational units, the introduction of special procedures for verifying digital evidence, reproducing its authenticity, and confirming the continuity of the chain of custody. It also substantiates the necessity of establishing a national digital evidence management system in accordance with international standards of the European Network of Forensic Science Institutes (ENFSI) and the Berkeley Protocol on Digital Open Source Investigations.

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

3D integration, a breakthrough technology to achieve Moore and More Than Moore, provides numerous benefits such as better performance, lower power consumption, and wide bandwidth by vertical interconnects and 3D stacking. These vertical interconnects enable design of high performance 3D Network-on-Chip (NoC) as a communication backbone for massive manycore platforms. However, existing 3D NoCs are still bottlenecked due to simple extension of 2D architectures without fully exploiting the advantages of the 3D integration. Moreover, the anticipated performance gain of 3D NoC-enabled manycore chips will be compromised due to potential failures of through silicon vias (TSVs) that are predominantly used as vertical interconnects. To address these problems, we explore a holistic design methodology starting from the physical layer to the overall interconnection architecture where the vertical data exchange takes place through contactless links using near field inductive coupling (NFIC).