A survey on interconnect encoding for reducing power consumption, delay, and crosstalk

Challenges and issues with the scaling of low-k/Cu interconnects in ultra-large-scale integration (ULSI) devices are reviewed, and the performance of interconnects is featured by considering the effect of the resistance and capacitance per unit interconnect length or the minimum grid length. The grid-scaled resistance-capacitance (GSRC) model is proposed to compare the interconnect performance at various technology nodes. Introduction of low-k films to reduce the line capacitance improves the per-grid value of the resistance-capacitance product, however, the abrupt increment of the line resistivity due to the small-size effect consumes the benefit of the capacitance beyond 32-nm-node. We also discuss power consumption in interconnects with different low-k structures based on experimental works. Continuous reduction of effective k-value (K eff) is needed to reduce the active power consumption. The way to reduce the interconnect resistance while keeping the interconnect reliability high is a key challenge, particularly for deeply scaled-down ULSIs.

Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption. Design/methodology/approach – The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain minimum or no crosstalk effects. The proposed encoding method uses the bus invert (BI) method. The proposed encoding methods are able to avoid the worst-case crosstalks while consuming lesser power during transmission in VLSI interconnects. Findings – It is observed that the proposed encoders reduced/eliminated the worst-case crosstalk by reducing SSN. The encoding method I also reduces Type 0 crosstalk by 100 per cent, while Type 1 crosstalk is reduced by 36.4 per cent and Type 2 is reduced by 16.8 per cent. The average simultaneous switching is reduced by 51.1 per cent. Similarly, encoding method II reduces switching activity by 10.3 per cent, whereas the coupling activity is reduced by 35.4 per cent. Furthermore, encoding method II also reduced Type 0, Type 1 and Type 2 crosstalk by 100, 36.9 and 27.1 per cent, respectively. Hence, the proposed encoding methods reduced the worst-case crosstalk completely. Research limitations/implications – In VLSI technology, the reduction in feature size and the increase in operating frequency are quite rapid. This leads to higher propagation delay, crosstalk and power dissipation through the interconnects. Most of the previously proposed encoders/decoders have turned out to be unsuitable for RLC modelled interconnects. Hence, the proposed encoder would be extremely useful for crosstalk reduction in newer operating conditions. Practical implications – The encoding method I identifies the harsh crosstalks, that is Type 0 and Type 1, in the inverted and non-inverted forms of incoming data with respect to the previous data. The data having minimum crosstalk in the inverted and non-inverted forms are only sent through the transmission line. The encoding method I also removes the worst-case crosstalk and simultaneously reduces other mild crosstalks. The removal of worst-case crosstalk improves the overall performance of the interconnect. The encoding method II identifies Type 2 crosstalk along with Type 0 and Type 1 similar to encoding method I. Furthermore, the encoding method II exhibits an improvement over method I in terms of reduction in crosstalk and power dissipation. Originality/value – This paper proposes a novel encoding method to reduce worst-case crosstalk effects that reduces SSN. The proposed encoding methods achieve their purpose of crosstalk reduction for several technology nodes.

Design and analysis of a low-swing driver scheme for long interconnects

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and

Low dielectric constant (Low-[Formula: see text]) films are used as inter layer dielectric (ILD) in nanoelectronic devices to reduce interconnect delay, crosstalk noise and power consumption. Tailoring capability of porous low-[Formula: see text] films attracted more attention. Present work investigates comparative study of xerogel, aerogel and porogen based porous low-[Formula: see text] films. Deposition of SiO2 and incorporation of less polar bonds in film matrix is confirmed using Fourier Transform Infra-Red Spectroscopy (FTIR). Refractive indices (RI) of xerogel, aerogel and porogen based low-[Formula: see text] films observed to be as low as 1.25, 1.19 and 1.14, respectively. Higher porosity percentage of 69.46% is observed for porogen-based films while for shrinked xerogel films, it is lowered to 45.47%. Porous structure of low-[Formula: see text] films has been validated by using Field Emission Scanning Electron Microscopy (FE-SEM). The pore diameters of porogen based annealed samples were in the range of 3.53–25.50 nm. The dielectric constant ([Formula: see text]) obtained from RI for xerogel, aerogel and porogen based films are 2.58, 2.20 and 1.88, respectively.

Interconnect delays, bandwidth and power consumption are increasingly dominating IC performance due to increases in chip size and reduction in the minimum feature size, in spite of new materials like Cu with low-k dielectric. Thereby severely limiting chip performance unless a paradigm shift from present interconnect architecture is introduced. One such promising technique is three-dimensional (3-D) ICs with multiple active Si layers and vertical interconnects. This paper presents a comprehensive review of 3-D ICs with multiple semiconductor layers. It is shown that significant improvement in performance and reduction in wire-limited chip area can be achieved with 3-D ICs if some long horizontal interconnects can be replaced by short vertical inter-layer interconnects. We also address the thermal concerns due to increased power density for 3-D circuits. Finally, an overview of some of the processing techniques which can be used to fabricate these circuits, is reviewed.

For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods are based on either (i) inserting dedicated interconnect selftest structures (leading to significant area overhead), or (ii) using existing logic BIST structures (e.g., LFSRs), which often result in poor defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concerti. In this paper we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing LFSR structures but generates high-quality tests for interconnect crosstalk defects, while minimizing area overhead and interconnect power consumption. On applying LI-BIST to a DSP chip, we achieved crosstalk defect coverage of 99.7% for the interconnects and single stuck-at-fault coverage of 91.36% for the logic cores, while incurring an area overhead of only 4% over conventional logic BIST.

The crosstalk noise induced on a net depends on its wire size, its driver size and the sizes of the aggressor gates driving its coupled nets. The problem of crosstalk noise optimization at post-route level is difficult due to the cyclic dependency on aggressor and victim driver sizes, resulting in a conflicting situation. Game theory provides a natural framework for handling conflicting objectives and allows simultaneous optimization of multiple parameters. The formulation of a convex objective function is a requirement in order to obtain better optimization in a game theoretic framework. This property is exploited to solve the cyclic dependency of crosstalk noise on its gate and wire sizes, while modeling the problem of simultaneous optimization of interconnect delay and crosstalk noise. A game is modeled with the crosstalk noise and interconnect delay of the chosen net as the players, the possible gate and wire sizes as the strategy set and the analytical expressions for crosstalk noise and interconnect delay as their respective expected payoffs. The time and space complexity of the proposed integrated sizing algorithm is linear in terms of the number of gates and wires in the design. Experimental results on several medium and large open core designs indicate average improvements of 27.52% and 34.03% for interconnect delay and crosstalk noise respectively, achieved by game theoretic gate sizing based on noise criticality over and above the optimization from the Cadence place and route tools without any area overhead or the need for rerouting

The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. We study the trends of interconnect power consumption based on current and future technology node parameters. We show that 20%-30% of the power is consumed by interconnect resistance in optimally buffered global interconnect systems. We also study the analysis method based on a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is addressed. The theoretical results can be used for any kind of linear circuit, including RLC circuits.

Wave-pipelined intra-chip signaling for on-FPGA communications

Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on Chip (NoC) interconnect for a 3D SoC that not only meets the application performance constraints, but also the constraints imposed by the 3D technology, is a significant challenge. In this work we present a design tool, SunFloor 3D, to synthesize application-specific 3D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components on to the 3D layers and performs a placement of them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3D and 2D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3D NoC when compared to the corresponding 2D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.

Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data coding for interconnect power and timing optimization has been introduced. In today’s SoCs these techniques are not efficient anymore due to their codec complexity or to their unrealistic experimentations. Based on some realistic observations on interconnect delay and power estimation, the spatial switching technique [1] is proposed. It allows the reduction of delay and power consumption (including extra power consumption due to codecs) for on-chip buses. The concept of the technique is to detect all cross-transitions on adjacent wires and to decide if the adjacent wires are exchanged or not. Results show the spatial switching efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12% for a 5-mm bus and more if buses are longer.KeywordsPower ConsumptionMetal LayerPower Consumption ReductionSwitching BlockAdjacent WireThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

As the device dimension is scaled down, interconnect RC delay becomes dominant performance limiter in high-performance VLSIs. Another issue in the submicron interconnects is a drastic increase of coupling capacitance due to the higher aspect ratio to reduce the interconnect resistance. The increase of the coupling capacitance degrades signal integrity, inducing noise problems and delay fluctuation problems. Buffer insertion (repeater insertion) is one of the most effective ways to decrease the interconnect delay. The original buffer insertion, however, cannot be applied to bi-directional buses because the buffer is uni-directional in nature. Some circuit configurations that can be applied to bi-directional buses have been proposed. These circuits turn out to be prone to malfunctions when there is a noise from adjacent lines in scaled down interconnect systems where capacitive coupling is large. A new buffer insertion scheme for bi-directional buses, namely the dual-rail bus (DRB) scheme, which does not have noise problems is proposed and measured in this paper. Another proposal is on a high-speed buffer insertion scheme for uni-directional buses by making use of staggered firing. The staggered firing bus (SFIB) is proposed and measured.

Track assignment is a critical step between global routing and detailed routing in modern VLSI chip designs. Crosstalk, which is largely decided by wire adjacency, has significant impact on interconnect delay and circuit performance. Therefore, the amount of crosstalk should be restrained in order to satisfy timing constraints. In this work, a novel track assignment algorithm is proposed to reduce crosstalk-induced performance degradation. The problem is formulated as a Traveling Salesman Problem (TSP) and solved by a graph-based heuristic. Experimental results on the ISPD2011 benchmark circuits show that the violations on crosstalk bounds can be reduced by up to 99.56% compared to the conventional non-constraint-based heuristics.

Multipliers are used in arithmetic and logic unit (ALU) and the performance of multiplier greatly depends on the number of adder cells. A study and performance investigation of array multiplier using low-power 10T full adder is presented. One of the crucial circuits in all digital devices is the adder cell and it is used in ALU. In this work, various performance parameters including power consumption, delay, and power-delay product are compared with full adder, array multiplier using 10T full-adder and static energy-recovery full (SERF) adder-based techniques. Array multipliers realized that using 10T-based full-adder circuit consumes less power when compared to SERF techniques. Simulation results show that the power consumption of array multiplier using 10T full-adder and SERF technique is 673.7 µW and 1.042 mW, respectively, which is less than the power consumption of conventional array multiplier. The power consumption and delay of proposed Array Multiplier are obtained using 180nm CMOS process.