Integrated Gate and Wire Sizing at Post Layout Level

Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power and area optimization. However, finding the optimal gate sizing solution is NP-hard [1], and the suboptimality of sizing solutions has not been sufficiently quantified for each heuristic. Thus, the need for further research has been unclear. In this work, we describe a new benchmark generation approach for leakage power-driven gate sizing (the subject of the forthcoming ISPD-2012 contest) which constructs realistic circuit netlists with known optimal solutions. The generated netlists resemble real designs in terms of gate count, maximum path depth, interconnect complexity (Rent parameter), and net degree distributions. Using these benchmark circuits with known optimal gate size, we have studied the suboptimality of several leakage-driven gate sizing heuristics, including two commercial tools, with respect to key circuit topology parameters. Our study shows that common sizing methods are suboptimal for realistic benchmark circuits by up to 52.2% and 43.7% for V t-assignment and gate sizing formulations, respectively. The results also suggest that (1) commercial tools may still suffer from significant suboptimality, and/or (2) existing methods have "similar" degrees of suboptimality. Copyright 2012 ACM.

The trends in technology scaling have made nanometer designs highly susceptible to reliability threats like soft errors and crosstalk noise while uncertainty in process parameters have made the physical realization of devices and interconnects unpredictable. The limitations in manufacturing processes and the impact of environmental noise poses a major threat to the signal quality, and hence the realization of reliable, low-power, high performance designs with acceptable parametric yields is a challenging problem. Most noise analysis and prevention techniques reported in the literature target single noise sources. However, reliability issues like crosstalk noise and radiation induced soft errors are deeply inter-related. Further, manufacturing variations have decreased the efficacy of online detection and correction schemes used for traditional noise optimization. In this work, we have proposed a methodology for simultaneous optimization of soft error rate(SER), crosstalk noise and power of circuits with delay constraints under process variations. Soft errors are modeled using a novel first order analysis model while crosstalk noise is modeled at the logic level using clustering based on Rent's exponent. The proposed multi-metric gate sizing methodology have been formulated into a mathematical program and has been efficiently solved. Experimental results on ISCAS'85 benchmark circuits indicate significant improvements in SER, crosstalk noise and timing yield compared to the corresponding constrained optimization problems.

Increasing dominance of process variations in the nanometer designs are posing significant challenges for circuit design and optimization. The variations in parameters such as channel length and the gate oxide thickness impacts circuit delay and power. In this paper, we propose a new gate sizing algorithm using fuzzy mathematical programming (FMP) in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay, which is a function of gate sizes and the fan-outs of the gate, are represented using triangular fuzzy numbers with linear membership functions. The variation aware gate sizing problem is formulated as a fuzzy mathematical program to perform a delay constrained power minimization in the presence of variations. Initially, a deterministic optimization is performed by fixing the fuzzy parameters to the worst and the average case values and the results are used to convert the fuzzy optimization problem into a crisp non-linear problem which is then solved using a non-linear optimization solver. The above model with delay and power as constraints, maximizes the robustness, i.e., the variation resistance of the circuit and thus the yield. The proposed approach was tested on ISCAS '85 benchmarks and the results were validated for timing yield using monte-carlo simulations. The fuzzy approach yields significantly better results compared to stochastic programming based gate sizing approach with a comparable runtime.

Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact on the yield of the integrated circuits and need to be considered early in the design flow. Traditional corner based deterministic methods are no longer effective and circuit optimization methods require reinvention with a statistical perspective. In this paper, we propose a new gate sizing algorithm using fuzzy linear programming in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay which is a function of the gate sizes and the fan-outs of the gates are represented using triangular fuzzy numbers with linear membership functions. Initially, as a preprocessing step for fuzzy optimization, we perform deterministic optimizations by fixing the fuzzy parameters to the worst and the average case values, the results of which are used to convert the fuzzy optimization problem into a crisp nonlinear problem. The crisp problem with delay and power as constraints is then formulated to maximize the robustness, i.e., the variation resistance of the circuit. The fuzzy optimization approach was tested on ITC'99 benchmark circuits and the results were validated for timing yield using Monte Carlo simulations. The proposed approach is shown to achieve better power reduction than the worst case deterministic optimization as well as the stochastic programming based gate sizing methods, while having comparable runtimes.

With the continuous scaling down of very large scale integrated (VLSI) technologies and increased die size, the transistors are much smaller, and hence much faster. On the other hand, interconnects are narrower. So they are more resistive and slower in transmitting signals. This trend has led the interconnect delay to become a significant factor in determining the performance of VLSI designs. As the die size becomes larger, global interconnect length becomes longer. Thus, global interconnect delay is beginning to dominate a larger portion of the overall system performance. In order to take the impact of interconnect delay into account, it is very important to have computationally inexpensive and accurate interconnect delay models. The primary contribution of this thesis is to present two new interconnect delay models, called the Fitted Elmore Delay (FED) and the Improved Effective Capacitance Metric (IECM). The FED model is a simple, efficient and reasonably accurate interconnect performance estimation model. This model uses a curve fitting technique to approximate the accurate Hspice delay data. The functional form used in the curve fitting is derived based on the Elmore Delay (ED) model. Thus, our model has all the advantages of the Elmore Delay model. It has a closed form expression as simple as the ED model and is extremely efficient to compute. More importantly, it is significantly more accurate than the ED model. In fact, because of its striking similarity to the ED model, optimization of the delay with respect to the design parameters can be easily done. When applied to interconnect optimization techniques (i.e., wire sizing), the FED model is three to four times more accurate than the Elmore Delay model. On the other hand, like the ED model, the FED has the limitation of ignoring the resistive shielding problem. This problem occurs when the gate no longer sees the total net capacitance due to the high interconnect resistance. The Improved Effective Capacitance Metric (IECM) overcomes the resistive shielding problem. We adopt the methodology of computing the first three Taylor series coefficients of the driving-point admittance in the circuit. The IECM uses these Taylor coefficients to derive a closed form solution for the effective capacitance that captures the resistive shielding characteristics. The IECM can be implemented with similar simplicity as the Elmore Delay model. We have tested the IECM on a single-load circuit and multiple tree topologies. Experiments show that our model is significantly more accurate than

Due to the technology scaling down, process variation has become a crucial challenge on both interconnect delay and reliability. To handle the process variation, statistical optimization has emerged as a popular technique for yield improvement. As a relatively new technique, second-order conic programming (SOCP) has recently attracted very much attention in the literature for statistical circuit optimization. However, we observe significant limitations of SOCP in its flexibility, accuracy, and scalability for statistical circuit optimization, especially when interconnects are considered. We thus present in this paper an effective and efficient alternative for multi-constrained statistical circuit optimization by both gate and wire sizing using Lagrangian relaxation (LR). Compared with SOCP, experimental results show that our LRbased algorithm can achieve much better solution quality by reducing 21% area and obtain 560X speed-up over SOCP.

In this paper, statistical models for the efficient analysis of interconnect delay and crosstalk noise in the presence of back-end process variations are developed. The proposed models enable closed-form computation of means and variances of interconnect-delay, crosstalk-noise peak, and coupling-induced-delay change for given magnitudes of variation in relevant process parameters, such as linewidth, metal thickness, metal spacing, and interlayer dielectric (ILD) thickness. The proposed approach is based on the observation that if the variations in different physical dimensions are assumed to be independent normal random variables, then the interconnect behavior also tends to have a Gaussian distribution. In the proposed statistical models, delay and noise are expressed directly as functions of changes in physical parameters. This formulation allows us to preserve all correlations and can be very useful in evaluating delay and noise sensitivities due to changes in various physical dimensions. For interconnect-delay computation, the authors express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. They show that ignoring higher order terms in the resulting variational moments does not result in a loss of accuracy. Finally, these variability-aware moments are used in known closed-form delay and slew metrics to compute interconnect-delay probability density functions (pdfs). Similarly for coupling noise and dynamic-delay analysis, the authors rely on the linearity (Gaussian) assumption, allowing us to truncate nonlinear terms and express noise and dynamic-delay pdfs as linear functions of variations in relevant geometric dimensions. They compare their approach to SPICE-based Monte Carlo simulations and report the error in mean and standard deviation of interconnect delay to be 1% and 4% on average, respectively

In this paper, we first present an efficient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure is embedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As a result, the algorithm is able to obtain superior solutions.

The unified logical effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic gates and resistive wires is presented. The method provides conditions for timing optimization while overcoming the limitations of standard logical effort (LE) in the presence of interconnects. The condition for optimal gate sizing in a logic path with long wires is also presented. This condition is achieved when the delay component due to the gate input capacitance is equal to the delay component due to the effective output resistance of the gate. The ULE delay model unifies the problems of gate sizing and repeater insertion: In the case of negligible interconnect, the ULE method converges to standard LE optimization, yielding tapered gate sizes. In the case of long wires, the solution converges toward uniform sizing of gates and repeaters. The technique is applied to various types of logic paths to demonstrate the influence of wire length, gate type, and technology.

The authors are concerned with the optimisation of combinational logic circuits. The competing factors, active area and delay time, are considered in the optimisation. The total active area is assumed to be a linear function of the gate sizes. There is a critical path whose delay time, the longest delay time of the circuit, depends on the sizes of the individual gates. This path will change many times during the optimisation. The optimisation process is used to produce the trade-off curve. The proposed methodology is based on the optimisation of the circuit critical path. This is a gate sizing problem on those paths that define the delay time of a circuit. Given a drive size for all the gates of the circuit, the trade-off curve contains design space points of minimum delay time and active area. A variable-sized subset of the Boolean network is optimised. Only the gates in the circuit critical path are optimised. The gates in the Boolean network which are not in the critical path do not need to be optimised. An efficient method is proposed for updating the critical path as the trade-off curve is obtained. Performance comparison and results were obtained over the set of MCNC two-level and combinational multilevel benchmark circuits. The proposed methodology produces trade-off curves, in relatively large circuits, with a great reduction in number of variables and run-time compared with the original full problem. In the proposed method, the number of variables is reduced by a factor of up to 7.3 times relative to the original full problem. The run-time behaviour is excellent, with an improvement between 1.5 and 32.5 times less CPU time compared with computation of the full Boolean network. With a higher gate count of the circuit, there are greater improvements in both run-time and number of variables.

Standard cell libraries provide designers with a fixed set of well characterized logic blocks. As designs are pushed for high performance, low area, and low power, it is essential to have a, good standard cell library that can help achieve these goals. As gate sizing is crucial to timing, the number of gate sizes (drive strengths) available for each of the primitives is an important factor to be considered. While an infinite granularity of gate sizes is preferable to get the best entitlement, it is often impractical due to the huge cost associated with developing and maintaining libraries. It is therefore essential to find ways to achieve the best performance, power and area, with a, reasonable library size. In this paper we focus on the problem of finding out the optimal ratio of gate sizes to be selected. 65nm libraries were used for validating the claims on a real design and the results are presented in this paper

: This thesis considers two problems in computer-aided design of VLSI circuits: (1) discrete gate sizing and (2) timing-driven placement improvement. The discrete gate-sizing problem is described as follows. A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient solution algorithm for combinational circuits, we examine the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification. This is done by appropriately selecting a size for each gate in the circuit and by adjusting the delays between the central clock distribution node and individual flip-flops. Existing methods treat these two problems separately, which may lead to very suboptimal solutions in some cases. We develop a novel unified approach to tackle them simultaneously. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.

This chapter presents buffer insertion in interconnect with a set of possible buffer positions and a discrete buffer library. Buffers can reduce wire delay by restoring signal strength, in particular, for long wires. The dramatic buffer scaling undoubtedly generates large and profound impact to very large scale integrated circuit design. Based on L. P. P. P. van Ginneken’s algorithm, numerous extensions have been made, such as handling of multiple buffer types, trade-off with power and cost, addressing slew rate and crosstalk noise, and using accurate delay models and speedup techniques. For a general case of signal nets, which may have multiple sinks, van Ginneken’s algorithm is perhaps the first systematic approach on buffer insertion. In addition to buffer insertion, wire sizing is an effective technique for improving interconnect performance. Noise avoidance techniques must become an integral part of the performance optimization environment.

With the increase in the levels of on-chip integration, the number of functional units integrated onto a single chip is rapidly increasing and as a result, the logic delays are decreasing due to faster transistors. At the same time, the local interconnect delays improve because the physical size of the circuit blocks decrease and the local interconnect spans shorter distances. On the other hand, the global interconnect delay increases with the technology scaling. Multiple design criteria are considered during the interconnect design process, such as delay, power, bandwidth and noise. Performance of any VLSI circuit depends on the bandwidth, as it decreases with the increase in the length of interconnects. Depending on the frequency range of operation, on-chip interconnect can be modelled as lumped and/or distributed RC line for low frequency and as a distributed RLC segments for high frequency. At even higher frequency, of the order of above 10GHz, the shunt conductance needs to be considered for accurate interconnect modelling. In this paper, on-chip interconnect has been modelled as distributed RLCG transmission lines, based on which a crosstalk aware bandwidth estimation method has been proposed in the transform domain in the presence of both inductive as well as capacitive coupling. First, the amount of crosstalk noise that would be induced on the victim line due to the transiting aggressor line has been analytically derived and then from the crosstalk noise voltage, a closed form expression for bandwidth has been proposed for distributed RLCG VLSI interconnects. The calculated bandwidth has been compared with the results obtained from that of SPICE simulation. The simulation shows that the proposed model could result an average error of as low as 15% when compared to the SPICE simulation.

When operating frequency is over several gigahertz, the effect of inductance plays an important role and should be included for accurate and speed crosstalk noise analysis. And for new generation IC (Integrated circuit) design tools, the crosstalk noise analysis tools should consider the influence of process variations. In this paper, we propose coupled RLC crosstalk noise distributed parameter model with capacitive load termination. And we develop the framework that how to use the crosstalk noise model for process variations. Our results show that compare with HSPICE, the critical data errors of proposed model are within 1% and the relative errors occurred between calculated values for process variations and HSPICE Monte Carlo simulation values are less than 5%. The key features of the new model include: (1) The impact of inductance on crosstalk noise is considered; (2) The model can be used for process variations analysis; (3) The model reflect the effects of load capacitance directly; (4) The numerical inversion of Laplace transform is introduced for improving speed. So the proposed model meets the needs of future IC design both in speed and accuracy.