Bandwidth Modelling for Distributed On-Chip RLCG Interconnect Considering Coupling Effects

Recently, progress in the high‐density wiring technique on a printed circuit board (PCB) has been remarkable. Thus the problem of malfunctions due to crosstalk noise occurring on the signal line must be addressed. The authors have been developing the noise estimation system for PCB named NESSY and a program to calculate the capacitance of multiconductor system (CALCAP). In NESSY, the wiring pattern is divided into small segments, which comprise the equivalent element circuit. The partial capacitance of the printed pattern is calculated by solving the integral equation and using the image method in CALCAP. The crosstalk analysis of equivalent circuit was made by the circuit simulation program.Among the results of this analysis, crosstalk noise using the partial element equivalent circuit (PEEC) agrees quite well with the measurement. The crosstalk noise should be anticipated by the close coupling theory in the case of frequently used wiring (both the width of signal line and line spacing are less than 1 mm). The crosstalk noise voltage was relatively large in the case of impedance mismatching. The far end crosstalk noise, previously neglected in most cases, becomes especially large.

Since the first electrical integrated circuits (ICs), the level of integration has been increasing with the scaling down of transistors. Although it is possible to integrate a number of transistors in a single chip, however, the ICs suffers from a performance bottleneck. To eliminate the performance bottleneck, an on-chip optical interconnect system has been in the limelight. However, developments in on-chip interconnect system have been made slow progress due to the absence of efficient on-chip light sources. Germanium (Ge) is the promising material for the on-chip optical interconnect system. However, Ge is not suitable for light sources because of its poor light emission efficiency. Thus, an efficient light source is the only missing key for the on-chip optical interconnect system. Throughout this thesis, we discuss our achievements about the efficient Ge based light sources, which can pave the way towards the on-chip optical interconnect system.

The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and noise output for 7.5 nm technology node at global level, which take the in-phase and out-of-phase crosstalk into account. The results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage are 25.202 ns and 0.102 V for an interconnect length of 3000 µm, respectively. It is demonstrated that the ultra-low-k dielectric materials can significantly reduce delay time and crosstalk noise and increase transfer gain compared with the conventional SiO2 dielectric medium. Moreover, it is found that the coupled MLGNR interconnect under out-of-phase mode has a larger crosstalk delay and a lesser transfer gain than that under in-phase mode, and the peak noise voltage increases with the increase of the coupled MLGNR interconnect length. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of MLGNR interconnects.

The crosstalk noise induced on a net depends on its wire size, its driver size and the sizes of the aggressor gates driving its coupled nets. The problem of crosstalk noise optimization at post-route level is difficult due to the cyclic dependency on aggressor and victim driver sizes, resulting in a conflicting situation. Game theory provides a natural framework for handling conflicting objectives and allows simultaneous optimization of multiple parameters. The formulation of a convex objective function is a requirement in order to obtain better optimization in a game theoretic framework. This property is exploited to solve the cyclic dependency of crosstalk noise on its gate and wire sizes, while modeling the problem of simultaneous optimization of interconnect delay and crosstalk noise. A game is modeled with the crosstalk noise and interconnect delay of the chosen net as the players, the possible gate and wire sizes as the strategy set and the analytical expressions for crosstalk noise and interconnect delay as their respective expected payoffs. The time and space complexity of the proposed integrated sizing algorithm is linear in terms of the number of gates and wires in the design. Experimental results on several medium and large open core designs indicate average improvements of 27.52% and 34.03% for interconnect delay and crosstalk noise respectively, achieved by game theoretic gate sizing based on noise criticality over and above the optimization from the Cadence place and route tools without any area overhead or the need for rerouting

Crosstalk noise has become an important issue as technology scales down for timing and signal integrity closure. Existing works to fix crosstalk noise are mostly done at the routing or post routing stage, which may be too late. Since placement determines the overall routing congestion, which correlates with the coupling capacitance, which in turn correlates with the crosstalk noise, placement shall be a good level to do early noise mitigation. The only existing work for the crosstalk aware placement (to our best knowledge) is by Lou and Chen (2004), which uses the coupling capacitance map to guide placement. However, crosstalk is determined not only by the coupling capacitance, but also by many other factors, such as the driver resistance of the victim net and the coupling location (near source vs near sink coupling) (Cong et al., 2001). We introduce a concept of noise map which takes those factors into account. Guided by this accurate noise map explicitly, we propose an incremental placement technique to mitigate noise without disturbing the global placement order. Our incremental placement has two key steps, namely noise aware cell inflation and local refinement. Experimental results on industrial circuits show that our approach is able to reduce the number of top noise nets by 25% and improve the timing (300ps on the worst slack), with no wire length penalty or CPU overhead. Our incremental approach is also able to maintain the placement stability.

Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device and wire process variations and temperature fluctuations. This margin is required to cover for a possible change in the critical path due to such variations. Moreover, a slower interconnect delay scaling with voltage compared to logic delay can cause the critical path to change from one operating voltage to another. With technology scaling, both process variation and interconnect delay are growing and demanding more margin to guarantee an error-free operation. Such margin is translated into a voltage overhead and a corresponding energy inefficiency. In this paper, a critical path emulator architecture is shown to track the changing critical path at different process splits by probing the actual transistor and wire conditions. Furthermore, voltage scaling characteristics of the actual critical path is closely tracked by programming logic and interconnect delay lines to achieve the same delay combination as the actual critical path. Compared to conventional open-loop and closed-loop systems, the proposed system is up to 39% and 24% more energy efficient, respectively. A 0.18-mum technology test chip is designed to verify the functionality of the proposed system showing critical path tracking of a 16times16 bit multiplier

As technology scaling is already enabling the integration of tens of hundreds of cores on a single chip, kilo-core chip multiprocessors (CMPs) are expected to be available within a decade. However, metallic-based on-chip interconnects may not scale to support kilo-core architectures due to increased hop count, high power dissipation, and increased latency. Emerging technologies such as silicon-photonics and wireless interconnects are under serious consideration as they show promising results for power-efficient, low-latency, and scalable on-chip interconnects. However, photonic technology suffers from scalability issues due to high component cost and complex arbitration while wireless technology lacks sufficient bandwidth for on-chip communication. In this paper, we propose an architecture called Optical-Wireless Network-on-Chip (OWN) that leverages the advantages of wireless and photonic technologies while circumventing the disadvantages of these two emerging technologies. Kilo-core OWN is designed such that one-hop photonic interconnect is used up to 64 cores (called a cluster). For communication beyond a cluster, one-hop wireless interconnect is proposed to enhance scalability. Both wireless and photonic bandwidths are efficiently shared using time division multiplexing (TDM). Moreover, packets routed across technologies are guaranteed to be deadlock-free. Our area results indicate that OWN requires 34% more area than hybrid-wireless architectures and 35.5% less area than photonic architectures. The energy/bit for OWN is 30.36% less than wireless and 13.99% more than photonic architecture. OWN demonstrates higher saturation throughput when compared to wired, wireless, and photonic technologies for synthetic network traffic.

Analytical compact form models for the signal transient and crosstalk noise of two-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms with eigen modes (i.e., even mode and odd mode). The signal transients and crosstalk noise expressions of two coupled lines are derived by using a wave-form approximation technique for the modal signals. It is shown that the models have excellent agreement with SPICE simulation.

In the physical chip design under the ultra-deep submicron (UDSM) process, interconnect delay, internal resistance drop (IR drop), and signal integrity (SI) has become the key factors affecting timing convergence and design cycle. This paper introduces a reconfigurable array processor architecture chip to solve the above problems. It discusses the requirements of the chip, the logic synthesis, and the physical design under the SMIC 55nm process in detail. First, four different timing optimization methods are employed to optimize the critical path that affects the timing, thus accelerating the execution time of the subsequent placement and routing. Secondly, the edge placement method based on data flow is adopted to reduce the interconnect length and delay of interconnection. Finally, the power network synthesis, placement, clock tree synthesis, and routing are completed. The results demonstrate that the working frequency can reach 320MHz. Meanwhile, the resource consumption is 80506 logic gates, and the chip area is 12mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The trends in technology scaling have made nanometer designs highly susceptible to reliability threats like soft errors and crosstalk noise while uncertainty in process parameters have made the physical realization of devices and interconnects unpredictable. The limitations in manufacturing processes and the impact of environmental noise poses a major threat to the signal quality, and hence the realization of reliable, low-power, high performance designs with acceptable parametric yields is a challenging problem. Most noise analysis and prevention techniques reported in the literature target single noise sources. However, reliability issues like crosstalk noise and radiation induced soft errors are deeply inter-related. Further, manufacturing variations have decreased the efficacy of online detection and correction schemes used for traditional noise optimization. In this work, we have proposed a methodology for simultaneous optimization of soft error rate(SER), crosstalk noise and power of circuits with delay constraints under process variations. Soft errors are modeled using a novel first order analysis model while crosstalk noise is modeled at the logic level using clustering based on Rent's exponent. The proposed multi-metric gate sizing methodology have been formulated into a mathematical program and has been efficiently solved. Experimental results on ISCAS'85 benchmark circuits indicate significant improvements in SER, crosstalk noise and timing yield compared to the corresponding constrained optimization problems.

This paper proposes a wave propagation based approach to derive crosstalk and delay between two coupled RLCG interconnects in the transform domain. The increase of clock frequency into the GHz range, coupled with longer length interconnects of small cross-section and low dielectric strength, can result in cross coupling effects between on-chip interconnects. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. In order to determine the effects that this cross talk will have on circuit operation, the resulting delays and logic levels for the victim nets must be computed. In this paper, we propose four reflection wave propagation based analytical model for estimation of crosstalk. An emphasis was made on the distributed nature of the RLCG model, thus underlining the effect of parasitic coupling inductance and conductance on present and future on-chip interconnects.

As high-speed digital and radio-frequency mixed-signal integrated circuits become increasingly common in product designs in industry, it is important for VLSI designers to be familiar with the challenges of chip testing and the behavior of circuit elements, including on-chip interconnect, at high frequencies. Expensive, specialized test equipment and software simulation packages for high-frequency chip testing and design are not always accessible for student research. This thesis documents the setup and characterization of a best-possible environment for high-frequency chip testing and data acquisition using existing laboratory equipment and resources. Experimental methodologies and measurement results of on-chip interconnect signal integrity and delay, ring oscillator noise and timing jitter, and time-domain reflectometry (TDR) testing are presented. Methods of modeling on-chip interconnect at high frequencies using field solvers and equivalent circuits are discussed. Lastly, the designs of single-ended and differential ring oscillators, for use in future voltage-controlled oscillator (VCO) and phase-locked loop (PLL) test chip designs, are presented and analyzed.

Field emission noise caused by capacitance coupling ESD in AMR/GMR heads

Design and analysis of a low-swing driver scheme for long interconnects

In this paper, statistical models for the efficient analysis of interconnect delay and crosstalk noise in the presence of back-end process variations are developed. The proposed models enable closed-form computation of means and variances of interconnect-delay, crosstalk-noise peak, and coupling-induced-delay change for given magnitudes of variation in relevant process parameters, such as linewidth, metal thickness, metal spacing, and interlayer dielectric (ILD) thickness. The proposed approach is based on the observation that if the variations in different physical dimensions are assumed to be independent normal random variables, then the interconnect behavior also tends to have a Gaussian distribution. In the proposed statistical models, delay and noise are expressed directly as functions of changes in physical parameters. This formulation allows us to preserve all correlations and can be very useful in evaluating delay and noise sensitivities due to changes in various physical dimensions. For interconnect-delay computation, the authors express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. They show that ignoring higher order terms in the resulting variational moments does not result in a loss of accuracy. Finally, these variability-aware moments are used in known closed-form delay and slew metrics to compute interconnect-delay probability density functions (pdfs). Similarly for coupling noise and dynamic-delay analysis, the authors rely on the linearity (Gaussian) assumption, allowing us to truncate nonlinear terms and express noise and dynamic-delay pdfs as linear functions of variations in relevant geometric dimensions. They compare their approach to SPICE-based Monte Carlo simulations and report the error in mean and standard deviation of interconnect delay to be 1% and 4% on average, respectively