A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations

Summary form only given. We consider the soft error sensitivity trends to various memory and logic components as they are scaled to smaller dimensions, higher integration densities, and lower operating voltages. We also review the three radiation mechanisms responsible for soft errors in the terrestrial environment and discuss the methods for characterizing radiation sensitivity and methods for extrapolating product soft error rate (SER) from accelerated tests - with a focus on the difficulties in using test chip SER data to derive actual product mean-time-to-failure from soft errors. We then focus on technology scaling trends for SER, showing that although DRAM bit SER has been reduced by about four to five times per generation, DRAM system failure rates remain unchanged because the amount of system memory has increased as fast as the reductions in DRAM bit SER. We also show that in deep sub-micron regime, the SRAM single bit SER saturates as a function of technology scaling. We also review techniques for reducing SER and conclude that error correction is the beast means of mitigating memory soft errors, and that in high reliability systems that employ error correction on all embedded memory, the product failure rate is limited by the sequential logic SER.

Near threshold computing (NTC) has significant role in reducing the energy consumption of modern very large scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This paper presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this paper, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture level analysis. Their experimental results show that in NTC, process variation and aging-induced SNM degradation is $2.5{\boldsymbol \times }$ higher than in the super threshold domain while SER is $8{\boldsymbol \times }$ higher. At NTC, the use of 8T instead of 6T SRAM cells can reduce the system-level SNM and SER by 14% and 22%, respectively. Besides, we observe that we can find the right balance between performance and reliability by using an appropriate cache organization at NTC which is different from the super threshold.

Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering of operating voltages. It is important for designers to be able to validate whether the Soft Error Rate (SER) targets of their design have been met, and help end users select the processor best suited to their reliability goals. The knowledge of the observable worst-case SER allows designers to select their design point, and bound the worst-case vulnerability at that design point. We highlight the lack of a methodology for evaluation of the overall observable worst-case SER. Hence, there is a clear need for a so called stress mark that can demonstrably approach the observable worst-case SER. The worst-case thus obtained can be used to identify reliability bottlenecks, validate safety margins used for reliability design and identify inadequacies in benchmark suites used to evaluate SER. Starting from a comprehensive study about how micro architecture-dependent program characteristics affect soft errors, we derive the insights needed to develop an automated and flexible methodology for generating a stress mark that approaches the maximum SER of an out-of-order processor. We demonstrate how our methodology enables architects to quantify the impact of SER-mitigation mechanisms on the worst-case SER of the processor. The stress mark achieves 1.4X higher SER in the core, 2.5X higher SER in DL1 and DTLB, and 1.5X higher SER in L2 as compared to the highest SER induced by SPEC CPU2006 and MiBench programs.

With the advances of semiconductor technology, the transistor size has been scaled down. This shrinkage makes the circuits more susceptible to the soft error, which is a wrong signal or data latched by storage elements. Thus, Soft Error Rate (SER) reduction has become an important issue recently. In this work, we propose two methods for minimizing this SER based on a circuit restructuring technique, IRredundancy Removal and Addition. Our first method is to rewire the higher SER gates while the second one is to restructure the subcircuits having higher soft error impacts. Experiential results show that the first method presents a reduction of 19.6\% SER and 9.9\% area on a set of ISCAS'85 and MCNC benchmarks on average. The second method gets 23.7\% soft error rate reduction with 9.6\% area overhead. By combining these two methods, we can rise the ratio of SER decreasing rate to area increasing rate up to 6.77. This ratio indicates our approach can reduce the SER within a small cost.

Describes the alpha-particle-induced soft errors in ECL logic circuitry. Soft-error 'hot' testing has been performed using 2.5-, 1.7-, and 1.3- mu m ECL gate arrays exposed to /sup 241/Am. Experimental results reveal that: (1) the soft errors in ECL logic circuitry are caused by two types of upsets, latch toggling and gate upsets in clock lines; (2) the soft error rate (SER) increases rapidly as feature size is scaled down; and (3) the SER increases rapidly as switching current is reduced. To overcome the degradation of soft-error tolerance, a soft-error hardened (SEH) circuit design technique employing a new driver configuration which prevents upsets of critical nodes from propagating to following gates is introduced. The SEH design has been implemented in the ECL gate arrays and verified to improve the SER by more than 10/sup 2/ times as compared with conventional circuits. >

As CMOS process technology scales below 100nm, the amount of charge required to upset a gate or memory cell (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</sub> ) is decreasing. Therefore, the probability that an energetic particle can generate enough charge to upset a circuit is increasing. Since these single event upsets do not damage the IC, they are called soft errors. With the proper detection and correction schemes, these particle induced soft errors can be mitigated in a way that does not impact the overall reliability of an electronic system. Since memory devices such as SRAM, DRAM and Flash comprise the largest gate counts in many designs, it is essential to understand their soft error mechanisms, characterize their soft error rates and develop effective mitigation techniques.

A cross-layer SER analysis in the presence of PVTA variations

While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this problem such as TMR require high area and power overhead. In this work, soft-error reliability is improved with minimal area overhead by careful, localized circuit restructuring. The key idea is to increase logic masking of errors by taking advantage of conditions already present in the circuit, such as observability don't-cares. We describe two circuit modification techniques to improve reliability: don't-care-based resynthesis and local rewriting. A key feature of these techniques is fast, on-the-fly estimation of soft error rate (SER) using our reliability evaluator AnSER. This tool is compared against prior SER evaluators and found to run orders of magnitude faster. We show empirically that our reliability-driven synthesis methods can reduce SER by 29-40% with only 5-13% area overhead.

This paper presents measurement results of alpha-particle-induced soft errors and multiple cell upsets (MCUs) in 65-nm 10 T SRAM with a wide range of supply voltage from 1.0 V to 0.3 V. We reveal that the soft error rate (SER) at 0.3 V is eight times higher than SER at 1.0 V, and the ratio of MCUs to the total upsets increases as the supply voltage decreases. The SER and ratio of MCUs with body-biasing are also described. In addition, we investigate an impact of manufacturing variability on the soft error immunity of each memory cell. In our measurement, a distinct influence of manufacturing variability is not observed even in subthreshold region.

A soft error rate analysis model for MOS dynamic RAM's is presented. The soft error rate can be quantitatively calculated by using a solution of the equations for diffusion and collection of alpha-particle-induced excess electrons and by combining a statistical treatment of alpha particle energy, incidence angles, and incidence positions with the noise charge calculation. The model is then applied to analyze a soft error experiment on 64-kbit dynamic RAM's. It is shown that soft error characteristics with regard to signal charge (critical charge), as well as alpha energy and incidence angle dependencies, can be definitely determined. The model can also be used to predict the location of soft errors in MOS dynamic RAM's.

In this paper, the Am-241 is used as an alpha particle radioactive source to investigate the soft error mechanism in 65-nm and 90-nm static random accessmemory (SRAM). Combining reverse analysis, TRIM and CREME-MC Monte Carlo simulation, the energy transport process, deposited energy spectrum and cross-section characteristics of alpha particles in the device are revealed. The results show that the soft error sensitivity of the 65-nm device is much higher than that of the 90-nm device, and no flipping polarity is found. According to the real-time measured soft error rate at an altitude of 4300 m in Tibetan Yangbajing area, the thermal neutron sensitivity and alpha particle soft error rate, the overall soft error rate of 65-nm SRAM used at sea level of Beijing city is 429 FIT/Mb, and the contribution from alpha particles is 70.63%. Based on the results of reverse analysis, a three-dimensional simulation model of the device is constructed to study the influence of the incident angle of alpha particles on the single event upset characteristics. It is found that the corresponding deposition energy value at the peak of the number of particles in the sensitive region decreases by 40% with the incident angle increasing from 0° to 60°. While the single event upset cross sectionincreases by 79% due to the apparent single event upset edge effect in a sensitive region of the 65-nm device.

The crosstalk noise induced on a net depends on its wire size, its driver size and the sizes of the aggressor gates driving its coupled nets. The problem of crosstalk noise optimization at post-route level is difficult due to the cyclic dependency on aggressor and victim driver sizes, resulting in a conflicting situation. Game theory provides a natural framework for handling conflicting objectives and allows simultaneous optimization of multiple parameters. The formulation of a convex objective function is a requirement in order to obtain better optimization in a game theoretic framework. This property is exploited to solve the cyclic dependency of crosstalk noise on its gate and wire sizes, while modeling the problem of simultaneous optimization of interconnect delay and crosstalk noise. A game is modeled with the crosstalk noise and interconnect delay of the chosen net as the players, the possible gate and wire sizes as the strategy set and the analytical expressions for crosstalk noise and interconnect delay as their respective expected payoffs. The time and space complexity of the proposed integrated sizing algorithm is linear in terms of the number of gates and wires in the design. Experimental results on several medium and large open core designs indicate average improvements of 27.52% and 34.03% for interconnect delay and crosstalk noise respectively, achieved by game theoretic gate sizing based on noise criticality over and above the optimization from the Cadence place and route tools without any area overhead or the need for rerouting

Accelerated soft error testing with proton beam was performed for 65 nm CMOS latches for the first time. The soft-error rate (SER) dependence on the physical layout was clarified. SER has dependence on the size of the diffusion regions since critical charge and charge collection is strong function of them. By optimizing it, SER can be reduced by 70%. The scaling trend of SER was also investigated. It is shown that SER degradation due to scaling can be suppressed by the moderate reduction of the supply voltage.

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

The rate of soft errors have been significantly increasing due to the aggressive scaling trends in the nanometer regime. Several circuit optimization techniques have been proposed in literature for preventing such transient faults, however, to the best of our knowledge, the reduction of soft error rate at the layout level has not been attempted in logic circuits. In this work, we show that transient glitches due to cosmic strikes can be sufficiently reduced by intelligently modifying the placement stage in cell based designs to selectively assign larger wirelengths to certain critical nets. Towards this, we propose a computationally efficient placement algorithm based on quadratic programming that significantly reduces the soft error rates of logic circuits. The algorithm tries to assign higher wirelengths for nets with low glitch masking probabilities for higher reduction in soft error rates (SER), while maintaining low delay and area penalty for the overall circuit. Experimental results on the ISCAS'85 benchmark circuits indicate that such a placement algorithm can significantly improve the soft error immunity in logic circuits without much delay and area overheads.