A soft error rate model for MOS dynamic RAM's

Summary form only given. We consider the soft error sensitivity trends to various memory and logic components as they are scaled to smaller dimensions, higher integration densities, and lower operating voltages. We also review the three radiation mechanisms responsible for soft errors in the terrestrial environment and discuss the methods for characterizing radiation sensitivity and methods for extrapolating product soft error rate (SER) from accelerated tests - with a focus on the difficulties in using test chip SER data to derive actual product mean-time-to-failure from soft errors. We then focus on technology scaling trends for SER, showing that although DRAM bit SER has been reduced by about four to five times per generation, DRAM system failure rates remain unchanged because the amount of system memory has increased as fast as the reductions in DRAM bit SER. We also show that in deep sub-micron regime, the SRAM single bit SER saturates as a function of technology scaling. We also review techniques for reducing SER and conclude that error correction is the beast means of mitigating memory soft errors, and that in high reliability systems that employ error correction on all embedded memory, the product failure rate is limited by the sequential logic SER.

Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering of operating voltages. It is important for designers to be able to validate whether the Soft Error Rate (SER) targets of their design have been met, and help end users select the processor best suited to their reliability goals. The knowledge of the observable worst-case SER allows designers to select their design point, and bound the worst-case vulnerability at that design point. We highlight the lack of a methodology for evaluation of the overall observable worst-case SER. Hence, there is a clear need for a so called stress mark that can demonstrably approach the observable worst-case SER. The worst-case thus obtained can be used to identify reliability bottlenecks, validate safety margins used for reliability design and identify inadequacies in benchmark suites used to evaluate SER. Starting from a comprehensive study about how micro architecture-dependent program characteristics affect soft errors, we derive the insights needed to develop an automated and flexible methodology for generating a stress mark that approaches the maximum SER of an out-of-order processor. We demonstrate how our methodology enables architects to quantify the impact of SER-mitigation mechanisms on the worst-case SER of the processor. The stress mark achieves 1.4X higher SER in the core, 2.5X higher SER in DL1 and DTLB, and 1.5X higher SER in L2 as compared to the highest SER induced by SPEC CPU2006 and MiBench programs.

Accelerated soft error testing with proton beam was performed for 65 nm CMOS latches for the first time. The soft-error rate (SER) dependence on the physical layout was clarified. SER has dependence on the size of the diffusion regions since critical charge and charge collection is strong function of them. By optimizing it, SER can be reduced by 70%. The scaling trend of SER was also investigated. It is shown that SER degradation due to scaling can be suppressed by the moderate reduction of the supply voltage.

With the advances of semiconductor technology, the transistor size has been scaled down. This shrinkage makes the circuits more susceptible to the soft error, which is a wrong signal or data latched by storage elements. Thus, Soft Error Rate (SER) reduction has become an important issue recently. In this work, we propose two methods for minimizing this SER based on a circuit restructuring technique, IRredundancy Removal and Addition. Our first method is to rewire the higher SER gates while the second one is to restructure the subcircuits having higher soft error impacts. Experiential results show that the first method presents a reduction of 19.6\% SER and 9.9\% area on a set of ISCAS'85 and MCNC benchmarks on average. The second method gets 23.7\% soft error rate reduction with 9.6\% area overhead. By combining these two methods, we can rise the ratio of SER decreasing rate to area increasing rate up to 6.77. This ratio indicates our approach can reduce the SER within a small cost.

An error-correcting code is described which can correct up to two soft errors on each work line within a DRAM (dynamic random-access memory) chip. Three dimensional DRAM chips with trench-type capacitors are vulnerable to double-bit soft errors when an alpha particle strikes at the intervening space between two vertical capacitors setting off a plasma discharge between them. The author presents a systematic study of soft-error related problems, and discusses the methodologies to correct the double-bit memory-cells upsets by using on-chip ECC (error-correcting code) circuits. A comprehensive study is made to estimate the improvement in soft-error rate (SER) and mean time between failure (MTBF) by the proposed ECC technique. The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed using combinational enumeration. >

In this paper, the Am-241 is used as an alpha particle radioactive source to investigate the soft error mechanism in 65-nm and 90-nm static random accessmemory (SRAM). Combining reverse analysis, TRIM and CREME-MC Monte Carlo simulation, the energy transport process, deposited energy spectrum and cross-section characteristics of alpha particles in the device are revealed. The results show that the soft error sensitivity of the 65-nm device is much higher than that of the 90-nm device, and no flipping polarity is found. According to the real-time measured soft error rate at an altitude of 4300 m in Tibetan Yangbajing area, the thermal neutron sensitivity and alpha particle soft error rate, the overall soft error rate of 65-nm SRAM used at sea level of Beijing city is 429 FIT/Mb, and the contribution from alpha particles is 70.63%. Based on the results of reverse analysis, a three-dimensional simulation model of the device is constructed to study the influence of the incident angle of alpha particles on the single event upset characteristics. It is found that the corresponding deposition energy value at the peak of the number of particles in the sensitive region decreases by 40% with the incident angle increasing from 0° to 60°. While the single event upset cross sectionincreases by 79% due to the apparent single event upset edge effect in a sensitive region of the 65-nm device.

Describes the alpha-particle-induced soft errors in ECL logic circuitry. Soft-error 'hot' testing has been performed using 2.5-, 1.7-, and 1.3- mu m ECL gate arrays exposed to /sup 241/Am. Experimental results reveal that: (1) the soft errors in ECL logic circuitry are caused by two types of upsets, latch toggling and gate upsets in clock lines; (2) the soft error rate (SER) increases rapidly as feature size is scaled down; and (3) the SER increases rapidly as switching current is reduced. To overcome the degradation of soft-error tolerance, a soft-error hardened (SEH) circuit design technique employing a new driver configuration which prevents upsets of critical nodes from propagating to following gates is introduced. The SEH design has been implemented in the ECL gate arrays and verified to improve the SER by more than 10/sup 2/ times as compared with conventional circuits. >

A novel component of dynamic random-access memory (DRAM) soft error, in addition to the previously known cell-failure component and the bit-line failure component, is reported. The error component, named the combined cell-bit line (CCB) failure mode, occurs when the cell and the bit line each collect radiation-induced charge which are individually insufficient to upset the cell, but which does cause an error in combination. Experimental results covering the three soft-error rate (SER) components (cell, bit line, and CCB) have been obtained using an Americium-241 source, over a wide range of cycle times from 75 ns to 30 mu s. The study indicates that, at short cycle times, CCB failure mode can dominate SER in high-density, high-speed dynamic memories.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents measurement results of alpha-particle-induced soft errors and multiple cell upsets (MCUs) in 65-nm 10 T SRAM with a wide range of supply voltage from 1.0 V to 0.3 V. We reveal that the soft error rate (SER) at 0.3 V is eight times higher than SER at 1.0 V, and the ratio of MCUs to the total upsets increases as the supply voltage decreases. The SER and ratio of MCUs with body-biasing are also described. In addition, we investigate an impact of manufacturing variability on the soft error immunity of each memory cell. In our measurement, a distinct influence of manufacturing variability is not observed even in subthreshold region.

The trends in technology scaling have made nanometer designs highly susceptible to reliability threats like soft errors and crosstalk noise while uncertainty in process parameters have made the physical realization of devices and interconnects unpredictable. The limitations in manufacturing processes and the impact of environmental noise poses a major threat to the signal quality, and hence the realization of reliable, low-power, high performance designs with acceptable parametric yields is a challenging problem. Most noise analysis and prevention techniques reported in the literature target single noise sources. However, reliability issues like crosstalk noise and radiation induced soft errors are deeply inter-related. Further, manufacturing variations have decreased the efficacy of online detection and correction schemes used for traditional noise optimization. In this work, we have proposed a methodology for simultaneous optimization of soft error rate(SER), crosstalk noise and power of circuits with delay constraints under process variations. Soft errors are modeled using a novel first order analysis model while crosstalk noise is modeled at the logic level using clustering based on Rent's exponent. The proposed multi-metric gate sizing methodology have been formulated into a mathematical program and has been efficiently solved. Experimental results on ISCAS'85 benchmark circuits indicate significant improvements in SER, crosstalk noise and timing yield compared to the corresponding constrained optimization problems.

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Nowadays, although the extensive time and efforts have concentrated on digital memory investigation, while Complementary Metal-Oxide-Semiconductor (CMOS) technology have been reduced down to nanometer feature sizes, many new challenges and roadblocks have become apparent in recent years. Low power configurations of new memory cells are proposed and evaluated by analyzing both static and dynamic behaviors. Furthermore, the hardened memory designs are also included in this dissertation to improve its robustness to the Soft Errors (SEs) and characterizations from different perspectives, such as Critical Charge and Soft Error Rate (SER).

The rate of soft errors have been significantly increasing due to the aggressive scaling trends in the nanometer regime. Several circuit optimization techniques have been proposed in literature for preventing such transient faults, however, to the best of our knowledge, the reduction of soft error rate at the layout level has not been attempted in logic circuits. In this work, we show that transient glitches due to cosmic strikes can be sufficiently reduced by intelligently modifying the placement stage in cell based designs to selectively assign larger wirelengths to certain critical nets. Towards this, we propose a computationally efficient placement algorithm based on quadratic programming that significantly reduces the soft error rates of logic circuits. The algorithm tries to assign higher wirelengths for nets with low glitch masking probabilities for higher reduction in soft error rates (SER), while maintaining low delay and area penalty for the overall circuit. Experimental results on the ISCAS'85 benchmark circuits indicate that such a placement algorithm can significantly improve the soft error immunity in logic circuits without much delay and area overheads.

As device geometries shrink to nanometers, increasing leakage current coupled with particle induced soft errors is exasperating the circuit reliability issues. In this paper, we first establish that independent solutions to these two problems can not lead to a good final solution. A more thoughtful and integrated design methodology is required to reconcile these two challenging issues. Next, we investigate the dependency of soft error rate on the body bias based leakage reduction method and introduce a novel body bias-dependent soft error model. We propose an optimization based and a heuristic driven approach to reduce leakage while satisfying the soft error rate limit. Our methods provide appropriate body bias configurations that lead to near-optimal total mean time to failure improvement of a circuit.

This paper presents an SRAM architecture employing a multiword-based ECC (MECC) scheme for soft error mitigation and a row virtual ground technique for array leakage reduction. The MECC combines four data words to form a 128 bit composite ECC word, two of which are interleaved in a row to mitigate cosmic neutron-induced multi-bit errors. The use of a composite word reduces the number of check-bits by 68%, however, requires a unique write operation that updates the check-bits by writing one data word while reading the other three data words. The ground potential of the composite word is raised to a nonzero value during retention in order to limit the leakage power consumption. A critical charge-based soft error rate (SER) model is proposed to estimate the resulting increase in the SER. Both the MECC scheme and the SER model are verified by implementing a 64-kb SRAM macro in 90 nm CMOS technology. The SRAM consumes 5.34 pJ energy with a data latency of 3.3 ns, thus showing up to 82% per-bit energy saving and 8x speed improvement over previously reported multiword ECC schemes. Accelerated neutron radiation test of the SRAM confirms 85% soft error correction by the MECC and 90% accuracy of the SER model.