Enhancing design robustness with reliability-aware resynthesis and logic simulation

Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backward‐traversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo‐based fault injection simulation on ISCAS'85 benchmark circuits.

An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects

Soft error simulations utilizing PHYSERD are presented. The comparison with the experimental data for 28 nm SRAM demonstrates that PHYSERD provides the high-accuracy estimation of soft error rate when combined with circuit simulation, while PHYSERD alone tends to overestimate soft error rate. We also analyze the contributions of transistors constituting SRAM and of secondary ions to soft error rate. We find that circuit simulation has a significant effect on these contributions and is essential to the prediction of soft error rate.

Soft error rate (SER) estimation is becoming more and more important since nanometer digital integrated circuits are getting increasingly vulnerable to soft errors. In this paper, a novel approach is proposed for soft error rate analysis of digital combinational circuit considering all masking factors. We introduce a concept called Probabilistic Vulnerability Window (PVW) which is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the circuit. A computation model is proposed to calculate PVW's for all circuit gate outputs. Using the computation model, the proposed method estimates the soft error rate of the circuit by computing the probabilistic vulnerability windows in a backward approach. Experimental results show that the proposed method increases the SER computation speed by 1000X, with less than 10% accuracy loss when compared to the Monte-Carlo based fault injection methods. The results also show than the proposed approach keeps its efficiency when it is applied for estimating the soft error rate considering various SET's with different initial widths while the runtime of traditional SER estimation methods increases rapidly in such cases.

Recent advanced high-speed communication systems, such as optical systems, require highest reliability at lowest possible power consumption. Thus, Pass Transistor Logic (PTL) is gaining lots of interest in these communication systems due to its power saving potential compared to traditional CMOS logic. However, due to the non-conventional logic structure, its susceptibility to radiation-induced soft errors is different from CMOS circuitry. Due to the unique generation and propagation of Single Event Transients (SETs) in PTL, different approaches for PTL soft error rate (SER) estimation are required. In this paper we propose a machine learning (ML) approach for SET propagation in PTL logic. Multi-layer feed-forward neural network together with support vector classifier (SVC) are used to build the SET pulse width and pulse amplitude models. Bayesian optimization using Gaussian Processes is utilized to tune the hyperparameters of neural network. The experimental results on full adder (FA), which is the key component in many large cirucits such as ALU, and comparison with Monte Carlo (MC) spectre simulations confirm the accuracy and speed of the proposed method.

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering of operating voltages. It is important for designers to be able to validate whether the Soft Error Rate (SER) targets of their design have been met, and help end users select the processor best suited to their reliability goals. The knowledge of the observable worst-case SER allows designers to select their design point, and bound the worst-case vulnerability at that design point. We highlight the lack of a methodology for evaluation of the overall observable worst-case SER. Hence, there is a clear need for a so called stress mark that can demonstrably approach the observable worst-case SER. The worst-case thus obtained can be used to identify reliability bottlenecks, validate safety margins used for reliability design and identify inadequacies in benchmark suites used to evaluate SER. Starting from a comprehensive study about how micro architecture-dependent program characteristics affect soft errors, we derive the insights needed to develop an automated and flexible methodology for generating a stress mark that approaches the maximum SER of an out-of-order processor. We demonstrate how our methodology enables architects to quantify the impact of SER-mitigation mechanisms on the worst-case SER of the processor. The stress mark achieves 1.4X higher SER in the core, 2.5X higher SER in DL1 and DTLB, and 1.5X higher SER in L2 as compared to the highest SER induced by SPEC CPU2006 and MiBench programs.

With the advances of semiconductor technology, the transistor size has been scaled down. This shrinkage makes the circuits more susceptible to the soft error, which is a wrong signal or data latched by storage elements. Thus, Soft Error Rate (SER) reduction has become an important issue recently. In this work, we propose two methods for minimizing this SER based on a circuit restructuring technique, IRredundancy Removal and Addition. Our first method is to rewire the higher SER gates while the second one is to restructure the subcircuits having higher soft error impacts. Experiential results show that the first method presents a reduction of 19.6\% SER and 9.9\% area on a set of ISCAS'85 and MCNC benchmarks on average. The second method gets 23.7\% soft error rate reduction with 9.6\% area overhead. By combining these two methods, we can rise the ratio of SER decreasing rate to area increasing rate up to 6.77. This ratio indicates our approach can reduce the SER within a small cost.

Efficient algorithms to accurately compute derating factors of digital circuits

Fast and accurate Soft Error Rate (SER) estimation is an important system design aspect. With the continued scaling of SRAM bit-cell dimensions and cell pitches, accurate modeling of the Multi-Bit Upset (MBU) component is becoming increasingly critical. This paper introduces MBU-Calc, a compact model for MBU SER estimation. The tool leverages Multi-Cell Upset (MCU) probabilities obtained through direct test-chip measurements. The main improvement with respect to prior published work [2] is the introduction of so-called Line Filling (LF) factors which enable more accurate projection and bucketing of silent data corruption (SDC) versus detected unrecoverable errors (DUE). The accuracy of the introduced model is demonstrated against measured MBU results.

Summary form only given. We consider the soft error sensitivity trends to various memory and logic components as they are scaled to smaller dimensions, higher integration densities, and lower operating voltages. We also review the three radiation mechanisms responsible for soft errors in the terrestrial environment and discuss the methods for characterizing radiation sensitivity and methods for extrapolating product soft error rate (SER) from accelerated tests - with a focus on the difficulties in using test chip SER data to derive actual product mean-time-to-failure from soft errors. We then focus on technology scaling trends for SER, showing that although DRAM bit SER has been reduced by about four to five times per generation, DRAM system failure rates remain unchanged because the amount of system memory has increased as fast as the reductions in DRAM bit SER. We also show that in deep sub-micron regime, the SRAM single bit SER saturates as a function of technology scaling. We also review techniques for reducing SER and conclude that error correction is the beast means of mitigating memory soft errors, and that in high reliability systems that employ error correction on all embedded memory, the product failure rate is limited by the sequential logic SER.

The rate of soft errors have been significantly increasing due to the aggressive scaling trends in the nanometer regime. Several circuit optimization techniques have been proposed in literature for preventing such transient faults, however, to the best of our knowledge, the reduction of soft error rate at the layout level has not been attempted in logic circuits. In this work, we show that transient glitches due to cosmic strikes can be sufficiently reduced by intelligently modifying the placement stage in cell based designs to selectively assign larger wirelengths to certain critical nets. Towards this, we propose a computationally efficient placement algorithm based on quadratic programming that significantly reduces the soft error rates of logic circuits. The algorithm tries to assign higher wirelengths for nets with low glitch masking probabilities for higher reduction in soft error rates (SER), while maintaining low delay and area penalty for the overall circuit. Experimental results on the ISCAS'85 benchmark circuits indicate that such a placement algorithm can significantly improve the soft error immunity in logic circuits without much delay and area overheads.

This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction. It addresses the role of device simulations, statistical simulation, analytical soft-error rate (SER) model development, and SER-model calibration. The resulting approach is easily automated and generic enough to be applied to any type of circuit for estimation of the nominal SER.

The trends in technology scaling have made nanometer designs highly susceptible to reliability threats like soft errors and crosstalk noise while uncertainty in process parameters have made the physical realization of devices and interconnects unpredictable. The limitations in manufacturing processes and the impact of environmental noise poses a major threat to the signal quality, and hence the realization of reliable, low-power, high performance designs with acceptable parametric yields is a challenging problem. Most noise analysis and prevention techniques reported in the literature target single noise sources. However, reliability issues like crosstalk noise and radiation induced soft errors are deeply inter-related. Further, manufacturing variations have decreased the efficacy of online detection and correction schemes used for traditional noise optimization. In this work, we have proposed a methodology for simultaneous optimization of soft error rate(SER), crosstalk noise and power of circuits with delay constraints under process variations. Soft errors are modeled using a novel first order analysis model while crosstalk noise is modeled at the logic level using clustering based on Rent's exponent. The proposed multi-metric gate sizing methodology have been formulated into a mathematical program and has been efficiently solved. Experimental results on ISCAS'85 benchmark circuits indicate significant improvements in SER, crosstalk noise and timing yield compared to the corresponding constrained optimization problems.

Describes the alpha-particle-induced soft errors in ECL logic circuitry. Soft-error 'hot' testing has been performed using 2.5-, 1.7-, and 1.3- mu m ECL gate arrays exposed to /sup 241/Am. Experimental results reveal that: (1) the soft errors in ECL logic circuitry are caused by two types of upsets, latch toggling and gate upsets in clock lines; (2) the soft error rate (SER) increases rapidly as feature size is scaled down; and (3) the SER increases rapidly as switching current is reduced. To overcome the degradation of soft-error tolerance, a soft-error hardened (SEH) circuit design technique employing a new driver configuration which prevents upsets of critical nodes from propagating to following gates is introduced. The SEH design has been implemented in the ECL gate arrays and verified to improve the SER by more than 10/sup 2/ times as compared with conventional circuits. >