Soft error rate estimation of combinational circuits based on vulnerability analysis

Soft error rate (SER) estimation is becoming more and more important since nanometer digital integrated circuits are getting increasingly vulnerable to soft errors. In this paper, a novel approach is proposed for soft error rate analysis of digital combinational circuit considering all masking factors. We introduce a concept called Probabilistic Vulnerability Window (PVW) which is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the circuit. A computation model is proposed to calculate PVW's for all circuit gate outputs. Using the computation model, the proposed method estimates the soft error rate of the circuit by computing the probabilistic vulnerability windows in a backward approach. Experimental results show that the proposed method increases the SER computation speed by 1000X, with less than 10% accuracy loss when compared to the Monte-Carlo based fault injection methods. The results also show than the proposed approach keeps its efficiency when it is applied for estimating the soft error rate considering various SET's with different initial widths while the runtime of traditional SER estimation methods increases rapidly in such cases.

Recent advanced high-speed communication systems, such as optical systems, require highest reliability at lowest possible power consumption. Thus, Pass Transistor Logic (PTL) is gaining lots of interest in these communication systems due to its power saving potential compared to traditional CMOS logic. However, due to the non-conventional logic structure, its susceptibility to radiation-induced soft errors is different from CMOS circuitry. Due to the unique generation and propagation of Single Event Transients (SETs) in PTL, different approaches for PTL soft error rate (SER) estimation are required. In this paper we propose a machine learning (ML) approach for SET propagation in PTL logic. Multi-layer feed-forward neural network together with support vector classifier (SVC) are used to build the SET pulse width and pulse amplitude models. Bayesian optimization using Gaussian Processes is utilized to tune the hyperparameters of neural network. The experimental results on full adder (FA), which is the key component in many large cirucits such as ALU, and comparison with Monte Carlo (MC) spectre simulations confirm the accuracy and speed of the proposed method.

An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects

Nano-scale digital integrated circuits are getting increasingly vulnerable to soft errors due to aggressive technology scaling. On the other hand, the impacts of process variations on characteristics of the circuits in nano era make statistical approaches as an unavoidable option for soft error rate estimation procedure. In this paper, we present a novel statistical Soft Error Rate estimation framework. The vulnerability of the circuits to soft errors is analyzed using a newly defined concept called Statistical Vulnerability Window (SVW). SVW is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the given circuit. The SER is calculated using a probabilistic formulation based on the parameters of SVWs. Experimental results show that the proposed method provides considerable speedup (about 5 orders of magnitude) with less than 5 % accuracy loss when compared to Monte-Carlo SPICE simulations. In addition, the proposed framework, keeps its efficiency when considering a full spectrum charge collections (more than 36X speedups compared to the most recently published similar work).

While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this problem such as TMR require high area and power overhead. In this work, soft-error reliability is improved with minimal area overhead by careful, localized circuit restructuring. The key idea is to increase logic masking of errors by taking advantage of conditions already present in the circuit, such as observability don't-cares. We describe two circuit modification techniques to improve reliability: don't-care-based resynthesis and local rewriting. A key feature of these techniques is fast, on-the-fly estimation of soft error rate (SER) using our reliability evaluator AnSER. This tool is compared against prior SER evaluators and found to run orders of magnitude faster. We show empirically that our reliability-driven synthesis methods can reduce SER by 29-40% with only 5-13% area overhead.

Soft error simulations utilizing PHYSERD are presented. The comparison with the experimental data for 28 nm SRAM demonstrates that PHYSERD provides the high-accuracy estimation of soft error rate when combined with circuit simulation, while PHYSERD alone tends to overestimate soft error rate. We also analyze the contributions of transistors constituting SRAM and of secondary ions to soft error rate. We find that circuit simulation has a significant effect on these contributions and is essential to the prediction of soft error rate.

Efficient algorithms to accurately compute derating factors of digital circuits

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Fast and accurate Soft Error Rate (SER) estimation is an important system design aspect. With the continued scaling of SRAM bit-cell dimensions and cell pitches, accurate modeling of the Multi-Bit Upset (MBU) component is becoming increasingly critical. This paper introduces MBU-Calc, a compact model for MBU SER estimation. The tool leverages Multi-Cell Upset (MCU) probabilities obtained through direct test-chip measurements. The main improvement with respect to prior published work [2] is the introduction of so-called Line Filling (LF) factors which enable more accurate projection and bucketing of silent data corruption (SDC) versus detected unrecoverable errors (DUE). The accuracy of the introduced model is demonstrated against measured MBU results.

We propose a new methodology for soft error rate estimation using multiple sensitive volumes and machine learning. The proposed methodology assigns multiple sensitive volumes to a unit circuit (e.g. SRAM cell) and constructs a discriminator from TCAD simulations by machine learning. For each ion reproduced by radiation transport simulation, the discriminator judges whether an upset occurs or not, and consequently we can obtain soft error rate by counting the number of events judged as upset events. Advantages of the proposed methodology are: (1) empirical construction and adjustment of sensitive volume and critical charge is no longer necessary, (2) multiple transistors can be easily considered, and (3) event-wise accuracy can be improved. We confirmed the correlation between irradiation results and simulation results for 65-nm silicon on thin buried oxide (SOTB) SRAM. The estimation error was 7% without any empirical optimization of sensitive volume and critical charge.

The single event upset (SEU) mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time consuming and must be performed for each different circuit topology, incident particle and track. This work presents an accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to SEU. The key idea of this work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit, without the need to run circuit simulations. To accomplish the task, but single event transient generation and its propagation through circuit logic stages is characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse (bit flip) which may propagate to the next logic gate or memory element. The propagation of the transient pulse through each stage of logic until it reaches a memory element is also modeled. Both duration and amplitude of the transient pulse are attenuated as it propagates through the logic gates. A simple, first order model for the degradation of a transient pulse as it is propagated through a chain of logic gates is also proposed. The model considers the electrical masking properties of the logic gates through which the pulse propagates. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-tools, intending to make automated evaluation of MOS circuit sensitivity to SEU possible, as well as automated estimation of soft error rate

Susceptibility of modern ICs to radiation-induced faults constitutes a matter of great concern in the recent years. Particularly, the transient faults and their impact on the combinational logic remain an intriguing issue, since the evaluation of their behavior is quite significant, especially for critical systems, for the development of error-resistant techniques in design process. For an accurate estimation of Soft Error Rate both single and multiple transient faults should be regarded since the appearance of the latter is more noticeable as technology downscales. The proposed tool, i.e. SER estimator, is based on Monte-Carlo simulations, in order to obtain an accurate result, and takes advantage of placement information to identify the vulnerable parts of a circuit. Finally, the verification shows a fairly good accuracy compared with SPICE.

This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction. It addresses the role of device simulations, statistical simulation, analytical soft-error rate (SER) model development, and SER-model calibration. The resulting approach is easily automated and generic enough to be applied to any type of circuit for estimation of the nominal SER.

Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability Function (VF) derived from Verilog fault injection. This framework guides targeted Engineering Change Orders (ECOs), such as clock-net remapping, re-routing, and the selective insertion of SET filters, within a reproducible open-source flow (Yosys, OpenROAD, OpenSTA). A new analytical Soft Error Rate (SER) model for clock trees is also proposed, which decomposes contributions from the root, intermediate levels, and leaves, and is calibrated by SPICE-measured propagation probabilities, area, and particle flux. When coupled with throughput, this model yields a frequency-aware system-level Bit Error Rate (BERsys). The methodology was validated on a First-In First-Out (FIFO) memory, demonstrating a significant vulnerability reduction of approximately 3.35× in READ mode and 2.67× in WRITE mode. Frequency sweeps show monotonic decreases in both clock-tree vulnerability and BERsys at higher clock frequencies, a trend attributed to temporal masking and throughput effects. Cross-node SPICE characterization between 65 nm and 28 nm reveals a technology-dependent effect: for the same injected charge, the 28 nm process produces a shorter root-level pulse, which lowers the propagation probability relative to 65 nm and shifts the optimal clock-tree partition. These findings underscore the framework’s key innovations: a technology-independent, early-stage VF for ranking critical clock nets; a clock-tree SER model calibrated by measured propagation probabilities; an ECO loop that converts VF insights into concrete hardening actions; and a fully reproducible open-source implementation. The paper’s scope is architectural and pre-layout, with extensions to broader circuit classes and a full electrical analysis outlined for future work.

As the technology scales down, space radiation induced soft errors are becoming a critical issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout-based Single-Event Transient (SET) injection approach to evaluate the Soft Error Rate (SER) of large combinational circuits in Complementary Metal-Oxide-Semiconductor (CMOS) bulk technology. We consider the effect of ion strike location on the SET pulse width in this approach. Heavy-ion experiments on two different inverter chains are conducted to verify this layout-based SET injection approach. The simulation and experiment results show that this approach can fairly reflect the SET pulse width distribution. Furthermore, we compare the soft error number calculated by our proposed layout-based approach with the normal SET injection approach, and illustrate the detailed circuit response obtained by our proposed approach.