A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits

Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backward‐traversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo‐based fault injection simulation on ISCAS'85 benchmark circuits.

Soft error rate (SER) estimation is becoming more and more important since nanometer digital integrated circuits are getting increasingly vulnerable to soft errors. In this paper, a novel approach is proposed for soft error rate analysis of digital combinational circuit considering all masking factors. We introduce a concept called Probabilistic Vulnerability Window (PVW) which is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the circuit. A computation model is proposed to calculate PVW's for all circuit gate outputs. Using the computation model, the proposed method estimates the soft error rate of the circuit by computing the probabilistic vulnerability windows in a backward approach. Experimental results show that the proposed method increases the SER computation speed by 1000X, with less than 10% accuracy loss when compared to the Monte-Carlo based fault injection methods. The results also show than the proposed approach keeps its efficiency when it is applied for estimating the soft error rate considering various SET's with different initial widths while the runtime of traditional SER estimation methods increases rapidly in such cases.

Recent advanced high-speed communication systems, such as optical systems, require highest reliability at lowest possible power consumption. Thus, Pass Transistor Logic (PTL) is gaining lots of interest in these communication systems due to its power saving potential compared to traditional CMOS logic. However, due to the non-conventional logic structure, its susceptibility to radiation-induced soft errors is different from CMOS circuitry. Due to the unique generation and propagation of Single Event Transients (SETs) in PTL, different approaches for PTL soft error rate (SER) estimation are required. In this paper we propose a machine learning (ML) approach for SET propagation in PTL logic. Multi-layer feed-forward neural network together with support vector classifier (SVC) are used to build the SET pulse width and pulse amplitude models. Bayesian optimization using Gaussian Processes is utilized to tune the hyperparameters of neural network. The experimental results on full adder (FA), which is the key component in many large cirucits such as ALU, and comparison with Monte Carlo (MC) spectre simulations confirm the accuracy and speed of the proposed method.

Estimating the frequency of the elements in a data set is commonly needed in data analysis. With the increase of the size of the data sets, accurately computing the number of times that each element appears with a counter becomes impractical. Instead, the Count Min Sketch (CMS) is widely used in big data processing to estimate frequency due to its simplicity and small storage needs. However, soft errors caused by Single Event Transients (SETs) will affect the hardware implementation of the CMS, mainly the hash functions. In this paper, the effect of SETs on the hash functions of the CMS frequency estimate is analyzed theoretically in terms of overestimation probability, underestimation probability, and the equal probability, and further discussed for data with different frequency. Simulation results verify the correctness of the theoretical analysis and reveal several valuable conclusions. First, a large portion of SETs can be tolerated by the CMS itself, and the reliability of the CMS improves when larger number of arrays are used. Second, the average probability for overestimation and underestimation are almost the same, and decrease for larger numbers of arrays. Third, SETs are more likely to cause underestimation for the most frequent data elements. Finally, the overall effect of SETs on the CMS is slightly affected by the number of counters in each array, and seems to be independent of the distribution of the input sequence. The results and analysis presented in this paper provide a starting point for the design of efficient SET fault-tolerant schemes for the CMS.

Due to scaling induced effects, CMOS circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. Researchers mostly considered SE transients as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications such as avionics, military and medical applications, additional sources such as SE induced soft delays, clock jitters, false clock pulses and crosstalk effects need to be included in soft-error reliability analysis. As technologies advance, coupling effects among interconnects increasingly cause SE transients to contaminate electronically unrelated circuit paths, which can in turn increase the "SE susceptibility" of CMOS circuits. This work focuses on such coupling induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SE transient effects, and crosstalk contribution to soft error rate has been examined. In addition, the SE induced coupling delay effect has been studied and compared to radiation induced soft delay effect for various technologies. Results show that, in newer technologies, the SE coupling delay becomes quite comparable to soft delay effect, although caused indirectly by cross-coupling effects. In comparisons, the distributed nature of interconnects has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies.

While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this problem such as TMR require high area and power overhead. In this work, soft-error reliability is improved with minimal area overhead by careful, localized circuit restructuring. The key idea is to increase logic masking of errors by taking advantage of conditions already present in the circuit, such as observability don't-cares. We describe two circuit modification techniques to improve reliability: don't-care-based resynthesis and local rewriting. A key feature of these techniques is fast, on-the-fly estimation of soft error rate (SER) using our reliability evaluator AnSER. This tool is compared against prior SER evaluators and found to run orders of magnitude faster. We show empirically that our reliability-driven synthesis methods can reduce SER by 29-40% with only 5-13% area overhead.

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

As the technology scales down, space radiation induced soft errors are becoming a critical issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout-based Single-Event Transient (SET) injection approach to evaluate the Soft Error Rate (SER) of large combinational circuits in Complementary Metal-Oxide-Semiconductor (CMOS) bulk technology. We consider the effect of ion strike location on the SET pulse width in this approach. Heavy-ion experiments on two different inverter chains are conducted to verify this layout-based SET injection approach. The simulation and experiment results show that this approach can fairly reflect the SET pulse width distribution. Furthermore, we compare the soft error number calculated by our proposed layout-based approach with the normal SET injection approach, and illustrate the detailed circuit response obtained by our proposed approach.

Single event transients (SETs) stand out as one of the major causes of soft errors in nanoscale CMOS integrated circuits. To reduce the need for exhaustive circuit simulations in the design of radiation-hard integrated circuits, the cost-effective approaches for characterization and modeling of SET generation effects in standard logic cells are required. In this work, a SPICE-based methodology for characterization of SET generation effects, employing two different SET current models, is presented. Based on the acquired simulation results, the empirical models for the two main SET generation metrics (SET critical charge and SET pulse width) are derived. The SET generation models and the respective model parameters are intended to be used as inputs for the higher-level analysis of SET effects in digital circuits designed with the characterized standard logic cells. By storing the model parameters for each gate in the look-up table, instead of storing the raw data obtained from SPICE simulations, the amount of characterization data can be significantly reduced, allowing to speed up the subsequent SET analysis of a complex circuit.

In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which seriously affect the system's operation. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on logic circuits. This design style achieves SET mitigation by Strengthening the sensitive node using a likeness to feedback techniques. We have analyzed several techniques from hardening radiation at transistor level to a single event transient in 7nm FinFET devices. Simulation results have shown the proposed method has higher soft error robustness than the existing ones.

The drastic shrink in transistor dimensions is making circuits more susceptible to radiation-induced soft errors. While single-event upsets are beginning to be a concern for electronic systems fabricated with nanometer CMOS technology at the sea level, single-event transients (SETs) are also expected to be a serious problem for the upcoming technologies. Thanks to the high logic density and fast turnaround time, FPGAs are currently the main fabric used to implement electronic systems. However, to provide high logic density FPGA devices are also fabricated with state-of-the-art CMOS technology and thus are also susceptible to soft errors. This paper presents a novel technique to protect carry-select adders against SETs. Such technique is based on triple module redundancy (TMR) and explores the inherent duplication existing in carry-select adders to reduce resource overhead.

Soft error simulations utilizing PHYSERD are presented. The comparison with the experimental data for 28 nm SRAM demonstrates that PHYSERD provides the high-accuracy estimation of soft error rate when combined with circuit simulation, while PHYSERD alone tends to overestimate soft error rate. We also analyze the contributions of transistors constituting SRAM and of secondary ions to soft error rate. We find that circuit simulation has a significant effect on these contributions and is essential to the prediction of soft error rate.

Efficient algorithms to accurately compute derating factors of digital circuits

This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction. It addresses the role of device simulations, statistical simulation, analytical soft-error rate (SER) model development, and SER-model calibration. The resulting approach is easily automated and generic enough to be applied to any type of circuit for estimation of the nominal SER.

Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability Function (VF) derived from Verilog fault injection. This framework guides targeted Engineering Change Orders (ECOs), such as clock-net remapping, re-routing, and the selective insertion of SET filters, within a reproducible open-source flow (Yosys, OpenROAD, OpenSTA). A new analytical Soft Error Rate (SER) model for clock trees is also proposed, which decomposes contributions from the root, intermediate levels, and leaves, and is calibrated by SPICE-measured propagation probabilities, area, and particle flux. When coupled with throughput, this model yields a frequency-aware system-level Bit Error Rate (BERsys). The methodology was validated on a First-In First-Out (FIFO) memory, demonstrating a significant vulnerability reduction of approximately 3.35× in READ mode and 2.67× in WRITE mode. Frequency sweeps show monotonic decreases in both clock-tree vulnerability and BERsys at higher clock frequencies, a trend attributed to temporal masking and throughput effects. Cross-node SPICE characterization between 65 nm and 28 nm reveals a technology-dependent effect: for the same injected charge, the 28 nm process produces a shorter root-level pulse, which lowers the propagation probability relative to 65 nm and shifts the optimal clock-tree partition. These findings underscore the framework’s key innovations: a technology-independent, early-stage VF for ranking critical clock nets; a clock-tree SER model calibrated by measured propagation probabilities; an ECO loop that converts VF insights into concrete hardening actions; and a fully reproducible open-source implementation. The paper’s scope is architectural and pre-layout, with extensions to broader circuit classes and a full electrical analysis outlined for future work.