Standard Cell Printability Grading and Hot Spot Detection

Standard cells are the most critical and reusable elements to build up the whole chip, therefore foundry has to fully qualify the standard cell libraries to ensure their high quality when releasing to the customers for the chip design. To prevent pattern dependent lithographic difficulty in manufacturing is one target of standard cell qualification and becomes mandatory especially in advanced nodes due to tighter design rules and smaller design size. To identify a lithographic problematic standard cell, we have to take its surroundings within the optical diameter range into consideration because lithographic effects are intrinsically context-dependent. One critical step is to imitate standard cells placements in real designs and consider some important factors like VIA location as it impacts the mask shape directly. When the placement is completed, lithographic simulation is performed by LFD (Litho Friendly Design) to highlight risky locations. Every standard cell has to occur enough number of times to make sure the statistics of possibility of being a problem is reliable. The final statistics will instruct engineers on how to handle the problematic standard cells, either standard cell layouts have to be optimized or building a pattern database to prevent the abutments of particular standard cell combinations.

Self-Aligned Double Patterning (SADP) is being considered for use at the 10$nm$ technology node and below for routing layers with pitches down to ~50nm because it has better LER and overlay control compared to other multiple patterning candidates. To date, most of the SADP-related literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific design rules, we propose a coherent framework that uses Mixed Integer Linear Programming (MILP) and branch and bound method to simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the standard cells and maximizes the pin access flexibility for routing.

This paper presents a novel timing-driven global routing algorithm for standard cell (SC) layout design based on a critical network concept. The essence of this algorithm is different from that of the typical existing methods, such as the nets-based method and the critical-path-based method. The timing optimization strategy presented in this algorithm is more optimal than the typical existing ones, which makes it possible to reduce the delay in an overall survey. This algorithm has been implemented and tested by MCNC benchmark circuits in this paper. We compared the experimental results between our algorithm and the existing ones. The experimental results show that this algorithm is able to control the delay of the circuit efficiently, and causes little negative effect on other optimizing objectives.

Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iDTCO and block-level iDTCO. STC-level iDTCO, the main focus of this paper, consists of 4 major components; (1) full 3D process emulation with litho contour of standard cell (STC) layout, (2) auto-extraction of transistor compact model & parasitic RC extraction (PEX) in 3D, (3) performance-power-yield (PPY) analyzer, (4) multi-objective optimization of layout & process assumption (PA) to get best PPY. Applying our STC-level iDTCO flow to logic arch pathfinding, we could speed up our PPY analysis TAT by 5$\sim$10 times with good accuracy of >95%.

Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current complementary metal-oxide-semiconductor technologies. This paper explores how to fully exploit the layout dependence of stress enhancement and proposes a circuit-level, block-based, stress-enhanced optimization algorithm that uses stress-optimized layouts in conjunction with dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> assignment to achieve optimal power-performance tradeoffs. We begin by studying how channel stress and drive current depend on layout parameters such as active area length and contact placement, while considering all layout-dependent sources of mechanical stress in a 65 nm industrial process. We then investigate the three main layout properties that impact mechanical stress in this process and discuss how to improve stress-based performance enhancement in standard cell libraries. While varying the stress-altering layout properties of a number of standard cells in a 65 nm industrial library, we show that ?dual-stress? standard cell layouts (analogous to ?dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ?) can be designed to achieve drive current differences up to ~ 14% while incurring less than half the leakage penalty of dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> . Therefore, when the flexibility of ?dual-stress? assignment is combined with dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> assignment (within the proposed joint optimization framework), simulation results for a set of benchmark circuits show that leakage is reduced by ~ 24% on average, for iso-delay, when compared to dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> assignment. Since mobility enhancement does not incur the exponential leakage penalty associated with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> assignment, our optimization technique is ideal for leakage power reduction. However, our framework can also be used to achieve higher performance circuits for iso-leakage and our joint optimization framework can be used to reduce delay on average by ~ 5%. In both cases, the proposed method only incurs a small area penalty (<0.5%).

Flow of fixing of hot spot induced by optical variation among exposure tools is discussed for quick ramp-up of high volume products. To achieve robust pattern formation for optical variation, following hot spot detection and fixing approaches are introduced: i) at the design stage, hot spot detection within the optical variation space and hot spot fixing by layout modification or OPC optimization, ii) in order to efficiently detect hot spots within the optical variation space, lithography simulation by combinations of optical parameters determined by the design of experiment (DoE), iii) at the manufacturing stage, hot spot fixing by adjustment of optical parameters using the multi-variable optimization to match OPE between the primary and secondary exposure tool.

We propose a flow for routing nets within a standard cell that 1) generates candidate routes for point-to-point segments; 2) finds conflicts (electrical shorts and geometric design rule violations) between candidate routes; and 3) solves a SAT instance producing a legal and complete routing for all nets in the standard cell. This approach enables routing automation for cutting-edge process technology nodes. We present how to make this technique more effective by introducing pruning techniques to reduce the work required in all three steps. We also show how we can further optimize routing quality within the SAT formulation through the use of successively more stringent constraints. Recent improvements in the speed of SAT solvers make such a formulation practical for even complex standard cells. A routing tool based on our SAT formulation is currently being used to route real industrial standard cell layouts. It demonstrates acceptable runtime and 89% coverage of our industrial standard cell library, including scan flip-flops, adders, and multiplexers. We also observe a significant reduction in amount of metal2 routing in comparison with industrial hand-crafted standard cells.

Hot spots are residues comprising only a small fraction of interfaces yet accounting for the majority of the binding energy. These residues are critical in understanding the principles of protein interactions. Experimental studies like alanine scanning mutagenesis require significant effort; therefore, there is a need for computational methods to predict hot spots in protein interfaces. We present a new intuitive efficient method to determine computational hot spots based on conservation (C), solvent accessibility [accessible surface area (ASA)] and statistical pairwise residue potentials (PP) of the interface residues. Combination of these features is examined in a comprehensive way to study their effect in hot spot detection. The predicted hot spots are observed to match with the experimental hot spots with an accuracy of 70% and a precision of 64% in Alanine Scanning Energetics Database (ASEdb), and accuracy of 70% and a precision of 73% in Binding Interface Database (BID). Several machine learning methods are also applied to predict hot spots. Performance of our empirical approach exceeds learning-based methods and other existing hot spot prediction methods. Residue occlusion from solvent in the complexes and pairwise potentials are found to be the main discriminative features in hot spot prediction. Our empirical method is a simple approach in hot spot prediction yet with its high accuracy and computational effectiveness. We believe that this method provides insights for the researchers working on characterization of protein binding sites and design of specific therapeutic agents for protein interactions. The list of training and test sets are available as Supplementary Data at http://prism.ccbb.ku.edu.tr/hotpoint/supplement.doc. Supplementary data are available at Bioinformatics online.

Double Patterning is seen as the prime technology to keep Moore's law on path while EUV technology is still maturing into production worthiness. As previously seen for alternating-Phase Shift Mask technology[1], layout compliance of double patterning is not trivial [2,3] and blind shrinks of anything but the most simplistic existing layouts, will not be directly suitable for double patterning. Evaluating a production worthy double patterning engine with highly non-compliant layouts would put unrealistic expectations on that engine and provide metrics with poor applicability for eventual large designs. The true production use-case would be for designs that have at least some significant double patterning compliance already enforced at the design stage. With this in mind a set of ASIC design blocks of different sizes and complexities were created that were double patterning compliant. To achieve this, a set of standard cells were generated, which individually and in isolation were double patterning compliant, for multiple layers simultaneously. This was done using the automated Standard Cell creation tool Cadabra^TM [4]. To create a full ASIC, however, additional constraints were added to make sure compliance would not be broken across the boundaries between standard cells when placed next to each other [5]. These standard cells were then used to create a variety of double patterning compliant ASICs using iCCompiler^TM to place the cells correctly. Now with a compliant layout, checks were made to see if the constraints made at the micro level really do ensure a fully compliant layout on the whole chip and if the coloring engine could cope with such large datasets. A production worthy double patterning engine is ideally distributable over multiple processors [6,7] so that fast turn-around time can be achievable on even the largest designs. We demonstrate the degree of linearity of scaling achievable with our double patterning engine. These results can be understood together with metrics such as the distribution of the sizes of networks requiring coloring resulting from these designs.

This paper proposes a yield optimization method for standard cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield enhanced standard cells and the proposed method automatically creates yield enhanced cell layouts by decompacting the original cell layout using linear programming. We develop a novel accurate linear delay model which approximates the difference from the original delay and use this model to formulate the timing constraints into linear programming. Experimental results show that the proposed method can pick up the yield variants of a cell layout from the tradeoff curve of cell delay versus critical area and is used to create the yield enhanced cell library which is essential to realize yield-aware VLSI design flows.

In wireless sensor networks, sensor nodes are capable of not only measuring real world phenomena, but also storing, processing, and transferring these measurements. Many techniques have been proposed for storing and retrieving data in these networks. These methods are classified into three main categories. Data-centric storage is the most important one. The name comes from the fact that data's storage location is determined according to it's event type. However, most of the methods proposed in this category use a fixed event-location mapping or don't take nodes' resources into consideration. Therefore, storage nodes may experience unbalanced resource utilization problems which results into hot spot areas. We address this problem by proposing a dynamic mapping scheme which aims to reach two goals: First, to prolong network lifetime by efficient energy consumption and second, increasing quality of service by increasing data availability. The proposed method comes in two phases: First hot spot detection phase where storage nodes' status information is gathered at sink. Applying the proposed hot spot detection mechanism, sink detects a hot spotted node and alarms the node by sending a warning message to it. The hot spotted storage node receives the warning message and triggers the second phase named hot spot mitigation. In this stage it should transfer the responsibility of storing the event to another node in its' h hop neighborhood. Two metrics are considered in selecting a new storage node: 1) minimizing the total energy consumed for storing and retrieving the event 2) distributing network load evenly. The simulation presented here evaluates the proposed method in terms of network lifetime, data availability and energy consumption. The results show that the proposed method will delay hot spot effect with acceptable overhead.

Standard cell libraries are an important part of many of today's integrated circuit (IC) designs. The design of all digital ASICs (Application Specific Integrated Circuit) essentially involves the use of an ASIC standard cell library comprising logic functional primitives such as basic gate functions, complex combinational functions, sequential elements, arithmetic elements and 1I0s. In this paper the work involves, designing standard cell layouts with different cells using fixed height of standard cell template and characterizing standard cells using liberate and generating. lib file for standard cell. This Standard cell library was designed an industry academia chip collaborative project. By using Cadence virtuoso, liberate tools high performance with low power consumption standard cell library was developed.

In this paper, we propose an optimal pin assignment algorithm with improvement of cell placement in standard cell layout. The objective of the algorithm is to minimize the channel density by assigning nets to terminals of cells. If the number of possible terminal assignments for each cell is bounded by some constant r, then the proposed algorithm runs in linear time. In most practical cases, the value of r is relatively small, and thus the proposed algorithm is effective and efficient to reduce the chip area.

In this paper, we describe a way to build and explore auxiliary boundary constraints used to layout standard cells. It is required to build an electronic component of VLSI chip, a standard cell, given a set of constraints: geometrical design rules and additional electrical requirements. During layout of standard cells, additional constraints are formulated to avoid possible violations at cell boundaries when cells are abutted in a horizontal row. Current work proposes a flow to compute such auxiliary rules.

&amp;lt;p&amp;gt;Io is the Solar System body showing the largest number of active volcanic centers, primarily generated by tidal heating [1]. Many ground based and remote sensing observations have revealed&amp;amp;#160;spatial and temporal variabilities, important to define the characteristics of tidal heating and the mechanisms by which heat escapes from the interior [2, 3, 4].&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;The Jovian Infrared Auroral Mapper (JIRAM), the imager/spectrometer onboard JUNO mission, mainly devoted to the study of Jupiter&amp;amp;#8217;s atmosphere, had the opportunity to acquire data of the Galilean satellites, including Io.&amp;amp;#160;JIRAM is composed of a slit spectrometer covering a range of wavelengths between 2 and 5 &amp;amp;#956;m and an imager equipped with two filters, L and M, centered at 3.4 and 4.7 &amp;amp;#956;m, respectively [1].&amp;amp;#160;&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;In this work, we mapped the Io hot spots by using JIRAM M filter images from orbits 7, 9, 10, 16, 17, 18, 20, 24, 25, 26, 27, 32, 33, with a spatial scale ranging from &amp;amp;#8764; 48 up to ~150 km/pixel (Fig. 1), updating the work by [5]. For each orbit, we consider a set of images (referred to as &amp;amp;#8220;super images&amp;amp;#8221;) which contain the average radiance of several JIRAM contiguous observations. This approach minimizes the effects due to spurious pixels, reducing the detection of false hot spots [5].&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;JIRAM data cover almost the entire surface of Io, with a redundancy up to 43 super images per pixel in the northern and equatorial regions (Fig. 2), improving the observations of the polar areas.&amp;amp;#160;To identify Io hot spots, we first filtered each super image for emission angles &amp;gt; 75&amp;amp;#176;. Then, since JIRAM data have been acquired at different incidence angles, including Io dayside, nightside, and eclipse (Fig. 1), to select the hot spots, we divided the images in three categories: day (i&amp;amp;#8804; 70&amp;amp;#176;), dawn/dusk (70&amp;amp;#176; &amp;lt; i &amp;lt; 90&amp;amp;#176;) and night i&amp;amp;#8805; 90&amp;amp;#176;. For each super image, we calculated the median value of the radiance for the dayside, nightside and dawn/dusk background. Hence, we considered as hot spots&amp;amp;#8217; detection limit the radiance values larger than the median radiance for the night side, and median background radiance plus 0.003 for dawn/dusk and day side.&amp;amp;#160;&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;We identified 242 hot spots, many of which had already been included in other databases (e. g. [6, 7, 8, 9]). Among the hot spots revealed by JIRAM, 24 have not been observed before, and half of these are located at the poles.&amp;amp;#160; The comparison between our results and the last Io global heat flow power output map published by [8] suggests that the highest power heat flow hot spots are still active, indicating their activity lasts for decades or more, while a large part of the intermediate power heat flow hot spots are still present, as only 15 of them are not included in our map. We found the larger discrepancies in the lower heat flow hot spots, given that many of those listed as active by [8] have not been observed by JIRAM.&amp;amp;#160;&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;The study of Io hot spots variation and distribution, is worthwhile in helping to constrain the interior models and the magma distribution in its subsurface. The Io hot spots map presented here is the most up-to-date one produced by remote sensing datasets. The future JIRAM higher spatial resolution observations will be fundamental to extend and confirm our results, better distinguish close hot spots and improve our overall knowledge of Io volcanic processes and evolution.&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;&amp;lt;img src=&amp;quot;&amp;quot; alt=&amp;quot;&amp;quot; /&amp;gt;&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;&amp;lt;strong&amp;gt;Figure 1: &amp;lt;/strong&amp;gt;Example of Io JIRAM M filter images for the orbits JM 24 and 25.&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;&amp;lt;img src=&amp;quot;&amp;quot; alt=&amp;quot;&amp;quot; /&amp;gt;&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;&amp;lt;strong&amp;gt;Figure 2: &amp;lt;/strong&amp;gt;JIRAM M filter data coverage of Io for JIRAM orbits 10, 11, 16, 17, 18, 20, 24, 25, 26, 27, 32, 33.&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;&amp;lt;strong&amp;gt;Acknowledgments&amp;lt;/strong&amp;gt;&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;This work is supported by Agenzia Spaziale Italiana (ASI). JIRAM is funded by ASI contract 2016-353 23-H.0.&amp;amp;#160;&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;&amp;lt;strong&amp;gt;References&amp;lt;/strong&amp;gt;&amp;lt;/p&amp;gt; &amp;lt;p&amp;gt;[1] Peale, S. J.,&amp;amp;#160; et al., 1979, Science, 203. [2] Davies et al., 2015, Icarus, 262. [3] de Kleer et al., 2019, The Astronomical Journal, 158. [4] Adriani et al., 2017, Space Science Review, 213. [5] Mura, A., et al., 2020, Icarus, 241. [6] Lopes and Spencer, Eds, 2007, Praxis-Springer. [7] Williams, D. A., et al., 2011, Icarus, 214. [8] Veeder, G. J., et al., 2015, Icarus, 245. [9] Cantrall, C., et al., 2018, Icarus, 312.&amp;lt;/p&amp;gt;