Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization

In this study, we implemented an auto-correction method for layout of 45nm standard cells to get Design-for-Manufacturability (DFM) friendly design. The proposed method avoids lithography hotspot and particle defect, which are the source of systematic and random variation, by utilizing litho simulation and critical area analysis during optimization. In addition, to achieve maximum benefit of standard cell optimization, most of the recommended rules (RR) are applied to the standard cells. To assure the consistency of the optimization result, priority was given for each rule and the optimization is performed based on the priority. Using the proposed method, optimization time decreased tremendously compared to manual correction; therefore, the proposed layout optimization can handle thousands of standard cells with reasonable runtime. Verification results with manufacturing checking deck showed that DFM-friendly index improved by over 4.3% on optimized cells when compared to the original cells.

Prior to 90nm the main contributor to yield loss was particle contamination. Random particle defects were directly proportional to particle density and chip size. To maximize yield, manufacturing was done in clean rooms where particles were reduced to a minimum. Yield was then directly proportional to the chip size. At 90nm and below, systematic defects play major roles in yield. Two designs of the same size can result in very different yield. This paradigm shift is caused by the printability problems that are inherent to process technologies operating in the sub-wavelength regime. The technology for printing patterns on silicon has not kept up with Moore's law. The wavelength of lithography equipment is as much as 6 times larger than the silicon features. This results in greater variation on silicon, which directly affects yield. How the design is implemented is becoming as important as how small you make it. Even at the standard cell level different solutions can demonstrate increased sensitivity to particles, short, opens, gate leakage and other yield issue. We present in this paper a methodology for grading how well standard cells will print on silicon. Using standard cell layouts, we predict a silicon image under different process conditions and take CD measurements on these images. These measurements are converted into a printability factor for each cell. This printability factor is used to grade cells and identify which cells have the largest impact on printability and which should be optimized. To help with this optimization the measurements are also used to mark printability hot spots in the cell layouts.

Buffer insertion is an efficient technique in interconnect optimization. This paper presents a graph based algorithm for optimal buffer insertion under accurate delay models. In our algorithm, a signal is accurately represented by a finite ramp which is characterized by two parameters, shift time and transition time. Any accurate delay model, such as delay models based on the transmission line model and SPICE simulations, can be incorporated into our algorithm. The algorithm determines the optimal number of buffers and their locations on a wire such that some optimization objective is satisfied. Two typical examples of such optimization objectives are minimizing the 50% threshold delay and minimizing the transition time. Both can be easily determined in our algorithm. We show that the buffer insertion problem can be reduced to a shortest path problem. The algorithm can be easily extended for simultaneous buffer insertion and wire-sizing, and complexity is still polynomial. The algorithm can also be extended to deal with problems such as buffer insertion subject to transition time constraints at any position along the wire.

In this paper, we describe a way to build and explore auxiliary boundary constraints used to layout standard cells. It is required to build an electronic component of VLSI chip, a standard cell, given a set of constraints: geometrical design rules and additional electrical requirements. During layout of standard cells, additional constraints are formulated to avoid possible violations at cell boundaries when cells are abutted in a horizontal row. Current work proposes a flow to compute such auxiliary rules.

The multi-objective linear fractional programming is an interesting topic with many applications in different fields. Until now, various algorithms have been proposed in order to solve the multi-objective linear fractional programming (MOLFP) problem. An important point in most of them is the use of non-linear programming with a high computational complexity or the use of linear programming with preferences of the objective functions which are assigned by the decision maker. The current paper, through combining goal programming and data envelopment analysis (DEA), proposes an iterative method to solve MOLFP problems using only linear programming. Moreover, the proposed method provides an efficient solution which fairly optimizes each objective function when the decision maker has no information about the preferences of the objective functions. In fact, along with normalization of the objective functions, their relative preferences are fairly determined using the DEA. The implementation of the proposed method is demonstrated using numerical examples.

This paper presents a novel timing-driven global routing algorithm for standard cell (SC) layout design based on a critical network concept. The essence of this algorithm is different from that of the typical existing methods, such as the nets-based method and the critical-path-based method. The timing optimization strategy presented in this algorithm is more optimal than the typical existing ones, which makes it possible to reduce the delay in an overall survey. This algorithm has been implemented and tested by MCNC benchmark circuits in this paper. We compared the experimental results between our algorithm and the existing ones. The experimental results show that this algorithm is able to control the delay of the circuit efficiently, and causes little negative effect on other optimizing objectives.

A new design methodology targeted for core-based designs using parameterized macrocells (PMCs) is proposed. This methodology provides the flexibility for instance-based cores to be easily customized for application specifics. By using few scaling parameters to characterize a PMC, a macrocell can be instantiated in virtually any size depending on the required performance. Moreover, new macro delay and peak current models which are function of the PMC scaling parameters are proposed. These models enable accurate delay and peak current predictions at the subsystem/core level. The macro delay model is suitable for use in a delay optimizer to determine the optimum scaling parameters of individual PMC's in a core. The peak current model is useful for computing the peak current drawn by a PMC which allows efficient power rails sizing in order to address power grid reliability issues. A PMC library has been developed using the proposed methodology and used to design cores for communications applications. To demonstrate the effectiveness of the proposed methodology, a subsystem used in a channel decoder application was synthesized using this library where the individual PMC's were optimized for delay. The resulting custom-quality layout has an area of 50 /spl times/ 100 /spl mu/m/sup 2/ and a delay of 1.6 ns in 0.18 /spl mu/m, 1.8 V CMOS technology.

Folding, a key requirement in high performance cell layout, implies breaking a large transistor into smaller, equal sized transistors (legs) that are connected in parallel and placed contiguously with diffusion sharing. We present a novel technique, FCLIP, that integrates folding into the generation of optimal layouts of CMOS cells in the two dimensional (2D) style. FCLIP is based on integer linear programming (ILP) and precisely formulates cell width minimization as a 0-1 optimization problem. Folding is incorporated into the 0-1 ILP model by variables that represent the degrees of freedom that folding introduces into cell layout. FCLIP yields optimal results for three reasons: (1) it implicitly explores all possible transistor placements; (2) it considers all diffusion sharing possibilities among folded transistors; and (3) when paired P and N transistors have unequal numbers of legs, it considers all their relative positions. FCLIP is shown to be practical for relatively large circuits with up to 30 transistors, We then extend FCLIP to accommodate-and-stack clustering, a requirement in most practical designs due to its benefits to circuit performance. This reduces run times dramatically, making FCLIP viable for much larger circuits. It also demonstrates the versatility of FCLIP's ILP based approach in easily accommodating additional design constraints.

Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iDTCO and block-level iDTCO. STC-level iDTCO, the main focus of this paper, consists of 4 major components; (1) full 3D process emulation with litho contour of standard cell (STC) layout, (2) auto-extraction of transistor compact model & parasitic RC extraction (PEX) in 3D, (3) performance-power-yield (PPY) analyzer, (4) multi-objective optimization of layout & process assumption (PA) to get best PPY. Applying our STC-level iDTCO flow to logic arch pathfinding, we could speed up our PPY analysis TAT by 5$\sim$10 times with good accuracy of >95%.

Linear goal programming in estimation of classification probability

: The optimal timing of air-to-ground tasks is undertaken. Specifically, a scenario where multiple air vehicles are required to prosecute geographically dispersed targets is considered. The vehicles must perform multiple tasks on each target. The targets must be found, classified, attacked, and verified as destroyed. The optimal performance of these tasks requires cooperation amongst the vehicles such that critical timing constraints are satisfied. In this paper, an optimal task assignment and timing algorithm is developed, using a mixed integer linear program, or MILP, formulation. MILP can be used to assign all tasks to the vehicles in an optimal manner, including variable arrival times, for groups of air vehicles with coupled tasks involving timing and task order constraints. When the air vehicles have sufficient endurance, the existence of a solution is guaranteed.

With the fast development of regenerative braking technologies in modern transportation systems, it has become popular to take into account the regenerated electric energy of electric vehicles for energy-saving purposes. In railway transportation, it was found that given the monotonicity of the vehicle speed during an acceleration or braking process, a partial speed optimisation model can be set up and solved by Mixed Integer Linear Programming. Taking into account the similarity between road traffic and rail transportation, this paper aims to build up a linear programming model to optimise the speed trajectory of an electric vehicle (EV) during eco-approach and departure (EAD) to achieve a minimum energy cost. Three cases have been studied. First, we consider an optimisation model when the preceding vehicle is at a full-stop status, for example, when it is at a road crossing. We set up a case scenario with a constant running distance but different running time when the following EV initiates the car-following process. We will further investigate if the following EV has to use up all available running time before it fully stops behind the preceding vehicle. Second, an optimisation model is proposed by predicting the movement of the preceding vehicle. In this way, we are considering an optimisation problem with varying distance and time for the target car. Third, we try to consider a case where the following EV tries to accelerate to the same speed of the preceding vehicle under the time and distance constraints. The motivation of this paper lies on the successful applications of linear programming for partial train speed trajectory optimisation, the capability of regenerative braking of plug-in all electric vehicles (PA-EV) and speed trajectory optimisation in the application EAD. The proposed model takes advantage of its robustness, computational efficiency and readiness of potential on-line energy-saving applications in intelligent and connected vehicle systems.

In this paper, the impact of gate induced drain leakage (GIDL) on overall leakage of submicron VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down CMOS devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35 /spl mu/m CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield.

The differentiation of a cluster of nuclei and multi-nucleation is a critical issue in automated diagnosis systems. Due to the similarities between said clusters and malignant nuclei, misclassification of these regions can affect the automated systems' final decision. In this paper, a method for differentiating clusters from multi nucleated cells in histopathological images is proposed. Hepatocellular Carcinoma(HCC) and Dysplasia are characterized by cellular and nuclear enlargement, nuclear pleomorphism and multinucleation, which possess prominent threat Data was obtained from Global Hospital and Research Center from patients diagnosed with Hepatocellular Carcinoma and Dysplasia. This paper introduces a hybrid diagnosis method that uses texture, layout and context features of nuclei and cytoplastic cells in order to enhance the poor diagnosis of liver tumors in Infra Red (IR) images. We propose a Area based Adaptive Expectation Maximization(EM) that grows the clusters, which avoids the need for initial cluster selection in order to obtain texton maps of nuclei and cytoplasm. A linear regression model of nuclei and cytoplastic changes were built by incorporating the aforementioned features efficiently. The proposed method provides better classification and segmentation accuracy of nuclei and extra nuclear content in HCC and dysplasia, compared to the state-of-the-art methods like convolutional networks and classical methods like Adaptive K means and EM method in constant time. In conclusion, this system detects the malignant cells and the highly eligible precancerous cells which is cost effective and reproducible.

Standard cells are the most critical and reusable elements to build up the whole chip, therefore foundry has to fully qualify the standard cell libraries to ensure their high quality when releasing to the customers for the chip design. To prevent pattern dependent lithographic difficulty in manufacturing is one target of standard cell qualification and becomes mandatory especially in advanced nodes due to tighter design rules and smaller design size. To identify a lithographic problematic standard cell, we have to take its surroundings within the optical diameter range into consideration because lithographic effects are intrinsically context-dependent. One critical step is to imitate standard cells placements in real designs and consider some important factors like VIA location as it impacts the mask shape directly. When the placement is completed, lithographic simulation is performed by LFD (Litho Friendly Design) to highlight risky locations. Every standard cell has to occur enough number of times to make sure the statistics of possibility of being a problem is reliable. The final statistics will instruct engineers on how to handle the problematic standard cells, either standard cell layouts have to be optimized or building a pattern database to prevent the abutments of particular standard cell combinations.