Large-scale double-patterning compliant layouts for DP engine and design rule development

As the gap between the lithography wavelength and critical feature size has continued to increase, the semiconductor industry has had to adjust. Previously, scaling along Moore's Law had relied on improvement in lithography equipment, occasionally by reducing the wavelength and frequently by improving the effective numerical aperture. The wavelength used to define critical dimensions during much of the nineties was 248nm, with the industry switching to 193nm in the following decade. After 157nm technology failed to materialize due to technological challenges, the focus of next generation lithography (NGL) research shifted to EUV. Meanwhile, 193nm continued to be the workhorse for the continuation of Moore's Law. The next big equipment advancement came with immersion steppers, which increased the effective aperture of the lens, thereby capturing more of the diffraction orders in the imaging process. Moore's Law, however requires a significant innovation every two years! With optical lithography wavelength and effective lens aperture stretched to these limits, double patterning came to the rescue. By splitting the pattern into two, the burden on each mask was somewhat reduced, allowing a stitched pattern to scale. All through these changes, continued scaling also required a tighter co-optimization between process and design. As the image quality became generally weaker, greater restrictions were placed on the diversity of features that could be robustly patterned, leading to the proverbial increase in the heft of design rule manuals.All through these heroic efforts to continue Moore's Law, in order to reap the resulting benefits to the electronics industry, a relatively new field called Computational Lithography has been providing a helping hand. Computational Lithography comprises a broad set of techniques that use physics-based calculations to eke out greater lithographic performance from a given generation of steppers. This fertile field has recently introduced two advanced features: inverse lithography, and source-mask optimization. Such techniques have helped extend the life of optical lithography beyond previously forecast durations. At the same time, as other lithography technologies become more mature, much of the computational infrastructure developed to extend optical lithography will likely be used to optimize the newer technologies. This paper will provide some examples of how Computational Lithography is creating novel and affordable solutions to sustain the scaling trend.

As a design rule shrink down aggressively, various RETs (Resolution Enhancement Technology) have been developed to extend the resolution limits of lithography. Until now, next generation lithography has been focused on EUV technology. But no one can assure when EUV will be implemented. So, we must develop new technology with current immersion tool to catch up with aggressive design rule. One of those is DPT (Double Patterning Technology), however there are also many challenges to overcome such as patterning, overlay, hard mask etch and so on. The most critical issue would be overlay, because it affects CD (Critical dimension) uniformity directly. Therefore, overlay control is very important between 1 st DP layer and 2 nd DP layer. We utilized ArF immersion scanners for this experiment . In this paper, DP process flow, hard mask film dependency, align method dependency, efforts of new align key design and direct align analysis in DP overlay will be reported to understand and get better overlay accuracy than tool specification. It is needed to be verified that how much they take an effect on improving the DP overlay. Continuously we can conclude that most efforts in DPT should be focused on overlay control issue. KEY WORDS: Immersion, overlay, align, DPT (Double Patterning Technology)

Wave steering is a unified logic and physical synthesis scheme that algorithmically generates high-throughput circuits with fast turn-around times. Binary decision diagram (BDD)-type structures are altered to satisfy certain electrical constraints, embedded in silicon with pass transistor logic (PTL), and pipelined to very fine granularity using a novel two-phase clocking scheme. This direct PTL mapping of a logic representation provides good electrical estimations to a front-end tool like the logic synthesizer at an early phase of the design cycle. We apply our wave steering technique to high throughput computation-intensive datapath combinational circuits. We achieve an average speedup of 4.2 times compared to standard cell (SC) implementations of high performance arithmetic circuits at the cost of only about 76% average increase in area. The results look extremely encouraging; all the more so, considering that we also achieve an average reduction of 27% in latency and 15% in power compared to SC circuits.

Prior to 90nm the main contributor to yield loss was particle contamination. Random particle defects were directly proportional to particle density and chip size. To maximize yield, manufacturing was done in clean rooms where particles were reduced to a minimum. Yield was then directly proportional to the chip size. At 90nm and below, systematic defects play major roles in yield. Two designs of the same size can result in very different yield. This paradigm shift is caused by the printability problems that are inherent to process technologies operating in the sub-wavelength regime. The technology for printing patterns on silicon has not kept up with Moore's law. The wavelength of lithography equipment is as much as 6 times larger than the silicon features. This results in greater variation on silicon, which directly affects yield. How the design is implemented is becoming as important as how small you make it. Even at the standard cell level different solutions can demonstrate increased sensitivity to particles, short, opens, gate leakage and other yield issue. We present in this paper a methodology for grading how well standard cells will print on silicon. Using standard cell layouts, we predict a silicon image under different process conditions and take CD measurements on these images. These measurements are converted into a printability factor for each cell. This printability factor is used to grade cells and identify which cells have the largest impact on printability and which should be optimized. To help with this optimization the measurements are also used to mark printability hot spots in the cell layouts.

The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the art scanner will be limited to a numerical aperture of 1.35. Thus we cannot simply apply a shrink factor from the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is clearly established that early process for these layers will be performed by double patterning technique coupled with advanced OPC solutions. In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS) and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure good process control. This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored by the French government.

While lithography R&D community at large has already gotten the mind set for 32nm, all eyes are on 22nm node. Current consensus is to employ computational lithography to meet wafer CD uniformity (CDU) requirement. Resolution enhancement technologies (RET) and model OPC are the two fundamental components for computational lithography. Today's full-chip CDU specifications are already pushing physical limits at extreme lithography k₁ factor. While increasingly aggressive RET either by double exposure or double patterning are enabling imaging performance, for CDU control we need ever more accurate OPC at a greater computational efficiency. In this report, we discuss the desire for wanting more robust and accurate OPC models. One important trend is to have predictive OPC models allowing accurate OPC results to be obtained much faster, shortening the qualification process for exposure tools. We investigate several key parameters constitute to accuracy achievable in computational lithography. Such as the choice of image pixel size, numbers of terms needed for transmission cross coefficients (TCC), and "safe" ambit radius for assuring accurate CD prediction. Selections of image pixel size and "safe" ambit radius together determine % utilization for 2D fast Fourier transformation (FFT) for efficient full-chip OPC computation. For IC manufacturing beyond ArF, we made initial observations and estimations on EUV computational lithography. These discussions pave the way for developing a computational lithography roadmap extends to the end of Moore's Law. This computational lithography roadmap aims to be a complement for the current ITRS roadmap on what does it take to achieve CD correction accuracy.

In this paper, we describe a way to build and explore auxiliary boundary constraints used to layout standard cells. It is required to build an electronic component of VLSI chip, a standard cell, given a set of constraints: geometrical design rules and additional electrical requirements. During layout of standard cells, additional constraints are formulated to avoid possible violations at cell boundaries when cells are abutted in a horizontal row. Current work proposes a flow to compute such auxiliary rules.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Recently, <emphasis emphasistype="boldital">radio frequency identification</emphasis> (RFID) systems have gained popularity in manufacturing units, inventory, and logistics, as they represent an inexpensive and reliable solution for automatic identification. Moreover, RFID transponders are expected to become a key element in the ubiquitous computing scenario. Tags will likely be used to collect sensors data, enabling noninvasive environment monitoring. Low-cost passive UHF transponders are expected to play a major role in this context, due to extended read range capabilities. Within a passive tag, power harvested from the field irradiated by the reader during the communication should operate both digital control circuitry and potential sensing devices. Exploiting ultra-low power tag circuitry would provide sensing sections with higher energy, thus improving measurement performance. In this paper, the design of a novel circuit is presented, which implements the baseband processor of a UHF-RFID tag in compliance with the ISO 18000-6B protocol. Regardless of protocol selection issues, several power saving strategies are devised, both at the system and circuit levels, suitable for passive transponder implementation. Near-threshold operation has been exploited to attain ultra-low power consumption while keeping fair performance. A set of standard cells has been designed, suitable for the power-limited specific application. The proposed solution has been successfully checked by means of a physical implementation on CMOS 0.18 <formula formulatype="inline"><tex Notation="TeX">$ \mu{\hbox {m}}$</tex></formula> technology. Test chips have been characterized in terms of voltage and frequency operating range and power consumption figure has been extensively analyzed. Measurement results fully support the selected design approach: the baseband processor dissipates only 440 nW average power when operated at 800 kHz and 0.6 V. This extremely-low power consumption enables high-performance ubiquitous computing. </para>

As the critical dimension of devices is approaching the resolution limit of 193nm photo lithography, multiple patterning processes have been developed to print smaller CD and pitch. Multiple patterning and other advanced lithographic processes often require the formation of isolated features such as lines or posts by direct lithographic printing. The formation of isolated features with an acceptable process window, however, can pose a challenge as a result of poor aerial image contrast at defocus. Herein we report a novel Chemical Trimming Overcoat (CTO) as an extra step after lithography that allows us to achieve smaller feature size and better process window.

3-D stacked CMOS transistors offer an opportunity to enable further standard cell and SRAM scaling, making them a promising transistor architecture to extend Moore's law. We review state-of-the-art approaches for achieving 3-D CMOS stacking. The sequential approach is highlighted by fabricating Ge PMOS stacked via layer transfer on top of Si NMOS, and self-aligned approach is demonstrated by simultaneously fabricated NMOS-on-PMOS multi-nanoribbon Si transistors. Both approaches showcase a well-balanced CMOS inverter built from transistors in top and bottom device layers.

Multiple patterning technology has become an essential process. In the commonly used self-aligned multiple patterning process, the spacer should be dense at low temperatures and have a high elastic modulus. To meet these conditions, many thin-film deposition methods, such as plasma-enhanced atomic layer deposition, have been studied. We investigated remote plasma atomic layer deposition (RPALD) technology with a DC positive bias. After applying bias voltage to the plasma region, changes in the plasma properties, such as density and flux, were examined and applied to SiO2 deposition. When DC positive bias was applied, the sheath voltage decreased, causing an increase in the radical density, which contributed to the surface reaction. In an elastic recoil detection analysis, the application of 200 V reduced the hydrogen content of the film from 11.89% to 10.07% compared with no bias; an increase in SiO2 film density from 2.32 to 2.35 g cm−3 was also measured. The elastic modulus and hardness were shown to increase through a nano-indenter analysis and surface roughness improved with the suppression of energetic ions impinging on the film surface. Thus, the application of DC positive bias during the RPALD process effectively improved the physical, chemical, and mechanical properties of SiO2 film.

The semiconductor community is well aware of the challenges that exist in developing lithographic methods that can pattern features at sub-20 nm periodic feature spacing (pitch, L0). Optical lithography already utilizes complex multiple patterning schemes to overcome diffraction limitations at 193-nm exposure wavelengths, and the delayed insertion of EUV lithography will likely require the use of multiple patterning or other assistive processes to further reduce the achievable feature sizes. An alternative to these techniques employs the directed self-assembly (DSA) of block copolymers. Block copolymers (BCPs) can naturally micro-phase separate into morphologies such as lamellae, cylinders, spheres, and gyroids at length scales down to sub-10 nm dimensions. Using the ability of BCPs to micro-phase separate in conjunction with alignment methods such as graphoepitaxy and chemoepitaxy to produce well-ordered structures, a process referred to as DSA, offers a possible method for producing sub-20 nm features in conjunction with optical patterning processes at greatly reduced cost and complexity. One of the many challenges in implementing line-space type DSA processes is the lack of methods for effective modulation and tuning of the pattern pitch (L0) produced by a given BCP. Previous studies have shown that blending homopolymer into the BCP thin films can allow for tuning of both: (1) L0 to be larger than that provided naturally by the BCP's molecular weight (MW) and (2) the relative size line-space size ratio. However, this tuning ability comes at the expense of increased line edge roughness (LER) and line width roughness (LWR). It has also been shown that either higher or lower MW BCP can be blended into a primary BCP in order to modulate and tune the pattern pitch produced from the BCP mixture, but the effects of this BCP blending on pattern LER and LWR have not been explored or reported in detail. In this study, coarse-grained molecular dynamics simulations of BCP DSA on a chemoepitaxial underlayer were implemented to characterize the impacts that blending controlled amounts of two different MW BCPs together have on DSA pattern LER and LWR. The blends shown here had LER and LWR values as much as 20% higher than those of pure, monodisperse BCPs; however, reducing the MW difference between the 2 BCPs could reduce this effect.

Through the continuous scaling with extension of 193-immersion lithography, the multi-patterning process with the grid-based design has become nominal process for fine fabrication to relax tight pitch designs^[1]. In self-aligned type multiple patterning, 7 nm node gate pattern was reported^[2],[3] and it was become a focal point LER on core-pattern is essential category to control pattern placement variations. Though CD uniformity (CDU) on line pattern in self-aligned double patterning (SADP) is relatively stable caused in high thickness controllability of spacer deposition films, the variations of CDU and LER on first core pattern impinge the CDU on space and pitch pattern. In previous study, pattern fidelity of single exposure patterning was improved through photoresist smoothing process using direct-current superposition technique^[4],[5]. In this paper, we will report that photoresist smoothing work in an efficient way to pattern fidelity control in self-aligned type multiple patterning.

Self-Aligned Double Patterning (SADP) is being considered for use at the 10$nm$ technology node and below for routing layers with pitches down to ~50nm because it has better LER and overlay control compared to other multiple patterning candidates. To date, most of the SADP-related literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific design rules, we propose a coherent framework that uses Mixed Integer Linear Programming (MILP) and branch and bound method to simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the standard cells and maximizes the pin access flexibility for routing.

As lithographic technology is moving from single pattern immersion processing for 45nm node to double patterning for the next generation and onward to EUV processing, TEL is committed to understanding the fundamentals and improving our technology to enable customers to meet roadmap expectations. With regards to immersion and double patterning technology, TEL has presented a wide variety of technologies to advance the processing capability of our customers. With regards to EUV technology, we have previously presented work for simulation and modeling of an EUV resist system1 in order to further our understanding of the differences between resist performance from previous platforms and currently available EUV resists. As it's currently unknown which direction resist suppliers will take with regards to platform in order to surpass the current limitations in resolution, roughness and sensitivity trade off's, we need to consider the implications of such kinds of novel platforms to track processing capabilities. In this work, we evaluated two of the more promising materials, to determine processing sensitivities necessary for the development of new hardware and process applications. This paper details the initial study complete for understanding the track process parameters such as dissolution characteristics and the impact of film hydrophobicity. Fundamental processing knowledge from 193 and 248nm technology is applied to understand where processing deviates from known sensitivities and will require more development efforts.