Mechanical stress aware optimization for leakage power reduction

In recent years, process-induced mechanical stress has emerged as a useful manufacturing technique that enhances carrier transport and increases drive currents. This improvement in current has helped to compensate the decline of device scaling factors in parameters such as tox, Vth, and Vdd. In this work, we propose stress as a means to achieve optimal power-performance trade-off by combining stress-based, performance-enhanced standard cell assignment with dual-Vth, assignment. We study how stress-induced performance enhancements are affected by layout properties and improve standard cell layouts so that performance gains are maximized. We then develop a circuit-level, block-based, stress-enhanced optimization algorithm that includes all layout-dependent sources of mechanical stress. By combining the two performance enhancement techniques (stress-based and dual-Vth) for a set of benchmark circuits, we find that our stress-aware optimization, decreases leakage by ~24% on average, for iso-delay, when compared to dual-Vth assignment. Similarly, for iso-leakage, our optimization algorithm reduces delay on average by 5%. In both cases, the proposed method only incurs a small area penalty (< 0.5%).

Standard cells are the most critical and reusable elements to build up the whole chip, therefore foundry has to fully qualify the standard cell libraries to ensure their high quality when releasing to the customers for the chip design. To prevent pattern dependent lithographic difficulty in manufacturing is one target of standard cell qualification and becomes mandatory especially in advanced nodes due to tighter design rules and smaller design size. To identify a lithographic problematic standard cell, we have to take its surroundings within the optical diameter range into consideration because lithographic effects are intrinsically context-dependent. One critical step is to imitate standard cells placements in real designs and consider some important factors like VIA location as it impacts the mask shape directly. When the placement is completed, lithographic simulation is performed by LFD (Litho Friendly Design) to highlight risky locations. Every standard cell has to occur enough number of times to make sure the statistics of possibility of being a problem is reliable. The final statistics will instruct engineers on how to handle the problematic standard cells, either standard cell layouts have to be optimized or building a pattern database to prevent the abutments of particular standard cell combinations.

Mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in MOSFET channels, which results in enhanced carrier transport. New fabrication steps strive to increase carrier mobility which, consequently, increases both Ion and Ioff in CMOS devices. However, most stress-enhancement techniques are dependent on layout parameters and their effects can be exploited within standard cell library design. In this work, we propose a new standard cell library design methodology that shares VDD and VSS source/drain connections across standard cell boundaries. Such sharing allows for increased channel stress in both the corresponding device as well as its neighboring devices. Using an industrial 65 nm process and standard cell library, we show that our standard cell design methodology can be seamlessly integrated into current, state-of-the-art digital IC design flows. The new shared source/ drain technique improves critical path delay by 11% on average over a number of benchmarks for only a ~35% increase in leakage. Furthermore, stress-enhanced standard cell libraries offer a superior power/ delay tradeoff compared to dual-Vth across a wide range of operating points with reduced manufacturing costs. Specifically, our stress-enhanced library (with a single Vth) consumes ~2.5X less leakage than its dual-Vth counterpart.

Standard cell libraries are an important part of many of today's integrated circuit (IC) designs. The design of all digital ASICs (Application Specific Integrated Circuit) essentially involves the use of an ASIC standard cell library comprising logic functional primitives such as basic gate functions, complex combinational functions, sequential elements, arithmetic elements and 1I0s. In this paper the work involves, designing standard cell layouts with different cells using fixed height of standard cell template and characterizing standard cells using liberate and generating. lib file for standard cell. This Standard cell library was designed an industry academia chip collaborative project. By using Cadence virtuoso, liberate tools high performance with low power consumption standard cell library was developed.

Standard cell library is the basic for building blocks and SoC (system on chip). And design in current standard cell library always meets the most critical design rule, leading to tight lithography process window and hotspots easily. Besides, passing design rule check (DRC) cannot fully guarantee manufacturability. Lithography simulation check is an essential check item before tape out. It is significant to qualify the standard cell library at the most possible early stage in order to avoid design rework during the tape-out stage. For 14nm technology and below, hotspots appear both inside cell, abut regions of standard cells and pins for routing. Therefore, our paper puts forward a fast DFM-driven standard cell qualification approach to detect the hotspots inside cell and the potential defects from special kinds of pins and abutting standard cells. It can discover problems early and set constraints for placement and routing as early as possible for a fast product yield ramp-up.

Prior to 90nm the main contributor to yield loss was particle contamination. Random particle defects were directly proportional to particle density and chip size. To maximize yield, manufacturing was done in clean rooms where particles were reduced to a minimum. Yield was then directly proportional to the chip size. At 90nm and below, systematic defects play major roles in yield. Two designs of the same size can result in very different yield. This paradigm shift is caused by the printability problems that are inherent to process technologies operating in the sub-wavelength regime. The technology for printing patterns on silicon has not kept up with Moore's law. The wavelength of lithography equipment is as much as 6 times larger than the silicon features. This results in greater variation on silicon, which directly affects yield. How the design is implemented is becoming as important as how small you make it. Even at the standard cell level different solutions can demonstrate increased sensitivity to particles, short, opens, gate leakage and other yield issue. We present in this paper a methodology for grading how well standard cells will print on silicon. Using standard cell layouts, we predict a silicon image under different process conditions and take CD measurements on these images. These measurements are converted into a printability factor for each cell. This printability factor is used to grade cells and identify which cells have the largest impact on printability and which should be optimized. To help with this optimization the measurements are also used to mark printability hot spots in the cell layouts.

At advanced process nodes, lithography weak-points can act as major factors of yield losses in manufactured integrated circuits, especially under aggressive design rules. Thus, it is desirable to consider potential lithography weak-point issues during the phase of designing standard cells in order to improve manufacturability of integrated circuits. In this paper, we propose a partial pattern matching methodology, which is based on the use of a combinatorial K-partitioning technique, to identify all of potential lithography weak-points for standard cells in a given standard cell library. In addition, the proposed methodology adopts a pruning technique to minimize false violations, and uses a prioritization technique to prioritize tasks of modifying and/or redesigning standard cells. Compared with a conventional placement-and-routing based methodology, our experimental results show that the proposed methodology can accurately detect more potential lithography weak-points.

In this paper, we describe a new low-leakage standard cell based application-specific integrated circuit (ASIC) design methodology. This design is based on the use of modified standard cells, designed to reduce leakage currents (by almost two orders of magnitude) in standby mode and also allow precise estimation of leakage current. For each cell in a standard cell library, two low-leakage variants of the cell are designed. If the inputs of a cell during the standby mode of operation are such that the output has a high value, we minimize the leakage in the pull-down network, and similarly we minimize leakage in the pull-up network if the output has a low value. In this manner, two low-leakage variants of each standard cell are obtained. While technology mapping a circuit, we determine the particular variant to utilize in each instance, so as to minimize leakage of the final mapped design. We have performed experiments to compare placed-and-routed area, leakage and delays of this new methodology against Multithreshold CMOS (MTCMOS) and a regular standard cell based design style. The results show that our new methodology (which we call the "HL" methodology) has better speed and area characteristics than MTCMOS implementations. The leakage current for HL designs can be dramatically lower than the worst-case leakage of MTCMOS based designs, and two orders of magnitude lower than the leakage of traditional standard cells. An ASIC design implemented in MTCMOS would require the use of separate power and ground supplies for latches and combinational logic, while our methodology does away with such a requirement. Another advantage of our methodology is that the leakage is precisely estimable, in contrast with MTCMOS. Our primary contribution in this paper is a new low leakage design style for static CMOS designs. In addition, we also discuss techniques to reduce leakage in dynamic (domino logic) designs

At deep nano-scale nodes Silicon Nanowire field effect transistor (SiNW FET) imparts best performance. However, analysis of SiNW FET based circuit design is lacking in existing literature. In this study, we design a standard cell library for advanced 10nm lateral SiNW FET technology in super threshold regime. For this, we create a Verilog-A compact model. Our compact Verilog-A model includes all the short channel effect as well as the geometrical dependent parasitics, which are crucial for short channel devices. The model is well calibrated with TCAD and reported fabricated data. The standard cell library developed comprise INVERTER, NAND, and NOR gate cells. Finally, we compared the standard cell performance to FinFET based standard cell. We found that the Si NW CMOS based standard cells have ~3-4X, ~2-3X, and 3X performance in terms of power dissipation, energy-delay product and power delay product respectively compared to FinFET based designs.

Nowadays, Semi-custom design based on the standard cells is the mainstream design method for digital IC chip. In this thesis, the standard cell library is built and verified based on the SMIC 130nm technology, especially the optimization of a 1-bit full adder cell, during which the structure and layout of the full adder in the SMIC library is analyzed. As a result, the structure and size of the adder cell are improved better, which is simulated by H-spice. The comparison shows that the optimized adder is not only smaller in area, with width decreased by 0.82μm, but also have advantages in power consumption and timing, with energy delay product reduced by 7.7% .In the end, the s298 circuit in ISCAS Benchmark89 is used as the benchmark to complete the verification method of the standard cell library.

This paper presents a novel timing-driven global routing algorithm for standard cell (SC) layout design based on a critical network concept. The essence of this algorithm is different from that of the typical existing methods, such as the nets-based method and the critical-path-based method. The timing optimization strategy presented in this algorithm is more optimal than the typical existing ones, which makes it possible to reduce the delay in an overall survey. This algorithm has been implemented and tested by MCNC benchmark circuits in this paper. We compared the experimental results between our algorithm and the existing ones. The experimental results show that this algorithm is able to control the delay of the circuit efficiently, and causes little negative effect on other optimizing objectives.

We propose a flow for routing nets within a standard cell that 1) generates candidate routes for point-to-point segments; 2) finds conflicts (electrical shorts and geometric design rule violations) between candidate routes; and 3) solves a SAT instance producing a legal and complete routing for all nets in the standard cell. This approach enables routing automation for cutting-edge process technology nodes. We present how to make this technique more effective by introducing pruning techniques to reduce the work required in all three steps. We also show how we can further optimize routing quality within the SAT formulation through the use of successively more stringent constraints. Recent improvements in the speed of SAT solvers make such a formulation practical for even complex standard cells. A routing tool based on our SAT formulation is currently being used to route real industrial standard cell layouts. It demonstrates acceptable runtime and 89% coverage of our industrial standard cell library, including scan flip-flops, adders, and multiplexers. We also observe a significant reduction in amount of metal2 routing in comparison with industrial hand-crafted standard cells.

The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices

Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iDTCO and block-level iDTCO. STC-level iDTCO, the main focus of this paper, consists of 4 major components; (1) full 3D process emulation with litho contour of standard cell (STC) layout, (2) auto-extraction of transistor compact model & parasitic RC extraction (PEX) in 3D, (3) performance-power-yield (PPY) analyzer, (4) multi-objective optimization of layout & process assumption (PA) to get best PPY. Applying our STC-level iDTCO flow to logic arch pathfinding, we could speed up our PPY analysis TAT by 5$\sim$10 times with good accuracy of >95%.

In this article we present three 6-track standard cell libraries based on ASAP7 PDK which is extended to include three technologies, contacts over active gates (COAG), fin depopulation, and a diffusion break taking a space of one contacted poly pitch (CPP). All these three technologies are invented to reduce standard cell area and thus chip area. Experimental results show that fin depopulation solely can achieve 8.3% area saving, COAG brings about another 9.3%, and a diffusion break of 1 CPP adds another 2.5% more. These three technologies all together bring about 20% area saving when compared with that obtained by employing a 7.5-track cell library without excising these three technologies.