A Predictably Low-Leakage ASIC Design Style

Standard cell libraries are an important part of many of today's integrated circuit (IC) designs. The design of all digital ASICs (Application Specific Integrated Circuit) essentially involves the use of an ASIC standard cell library comprising logic functional primitives such as basic gate functions, complex combinational functions, sequential elements, arithmetic elements and 1I0s. In this paper the work involves, designing standard cell layouts with different cells using fixed height of standard cell template and characterizing standard cells using liberate and generating. lib file for standard cell. This Standard cell library was designed an industry academia chip collaborative project. By using Cadence virtuoso, liberate tools high performance with low power consumption standard cell library was developed.

The objective of this paper is to compare the power consumption, leakage voltage, leakage current and leakage power of 3-T DRAM while maintaining the competitive performance .The MTCOS and SVL technique is used in 3T DRAM to compare the performance. Multi-threshold CMOS(MTCMOS) is a CMOS chip which has a Transistor with multiple threshold voltage and SVL is a technique which used to reduce leakage during both the active and stand-by mode. DRAM was first invented by Dr. Robert Dennard in the year 1966. It is used in many advanced processor for chip instruction and data memory. It majorly contributes in power dissipation in off-state leakage current. In personal computers it is used as the main memory, workstations etc. The basic advantage of using DRAM is its simplicity in its structure. Keyword- DRAM; FinFET; CMOS; Leakage power; Leakage current; Frequency; Access time; MTCMOS; SVL; USVL; LSVL

This paper presented a simulation result of current comparator with low power and low leakage current using Multi-Threshold CMOS technique (MTCMOS). In all integrated circuit power consumption plays a vital role which is enumerated as top challenges for semiconductor in international technology. In given paper designing a circuit of comparator with MTCMOS circuit and without MTCMOS circuit and then compared these circuits with different parameters by changing voltage, frequency and temperature. In these CMOS current comparator circuit different parameters calculated like delay, power dissipation, signal to noise ratio, leakage power and leakage current. The multi-threshold complementary metal oxide semiconductor technique is proposed to reduce the power consumption and leakage current. After propagating the circuit the leakage power is reduced 89% and leakage current 73% using MTCMOS technique. The new comparator has been in 180nm technology using cadence tool. The simulation and analytical result show that the proposed circuit is correct.

The intention of this paper is to reduce leakage power and leakage current of 1-bit Full Adder while maintaining the competitive performance with few transistors are used (transistors count 10). A new high performance 1-bit Full Adder based on new logic approach is presented in this paper. MTCMOS technique which decreases the process variation on 1-bit Full Adder, the key of MTCMOS technique is applied on 1-bit Full Adder is to reduce the operating power, leakage power and leakage current. We investigate the use Multi-threshold CMOS (MTCMOS) technology provides low leakage and high performance operation by utilizing high speed, low Vth transistors for logic cells and low leakage, high Vth of transistor and show that it is particularly effective in sub threshold circuits and can eliminate performance variations with Low power. A 20 ns access time and frequency 0.05 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out 1-bit Full Adder.

The Multi-Threshold CMOS (MTCMOS) is a very attractive technique to reduce sub-threshold leakage currents during standby modes by utilizing high-V th power switches (sleep transistors). This technology is straightforward to use, because existing designs can be modified to become MTCMOS blocks by simply adding high-V th power supply switches. In addition, circuits can easily be placed in low leakage states at a fine grain level of control. For this reason, and because the time to market is critical, this technique gained the attention of the industry. Unlike the embedded MTCMOS designs discussed in Chapter 3, circuits employing high-V th sleep transistors do not require the re-designing of the original low-V th block.

: According to the ITRS roadmap, 70 percent of the area of a typical ASIC today is memory and this increases to over 90 percent by the end of the roadmap. Yet despite the fact that ASICs are becoming more memory-intensive, commodity memory and ASIC design and manufacturing technologies are still on divergent paths. In this report, we examine methodologies for the design of Memory-Based Structured ASICs (SASICs) that include large amounts of dense, on-chip memory, as well as multiple processing cores, networks-on-chip, and I/O modules. We investigate regular fabrics as a means for designing logic circuitry compatible with the lithographic constraints imposed by the memory array for subwavelength geometries. We also develop midrange and high-level tools for exploring tradeoffs in power, area, and timing of complex, multicore SASICs. The report concludes with recommendations for follow-on work in the area of patterned ASICs.

Standard library cells are basic building blocks for ASIC (application-specific integrated circuit) design, which improves designers' productivity through reduced design time and debugging. This paper presents the development of a CMOS standard cell library by the VTVT (Virginia Tech for VLSI and Telecommunications) Lab.

There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T and asymmetric 9T SRAM cells and calculated various design parameters using simulation of mentioned circuits at 70 nm. Here, to find better parametric compression, different cell ratios were also considered. From the simulation results, it is found that using MTCMOS design techniques, leakage current is effectively suppressed but on account of delay penalty. The delay penalty can also be minimized by selecting properly sized inverter cell. Keywords: SRAM, stability, SNM, MTCMOS Cite this Article Nidhi Tiwari, Vaibhav Neema, Rangra Kamal J et al. Comparative Analysis of Different SRAM Cells Architecture at 70 nm. Journal of VLSI Design Tools & Technology. 2018; 8(2): 33–41p.

ABSTRACTThe tremendous advancement in very large scale integration technology encourages chip designers to rely on commercial electronic design automation tools, offshore fabrication services, and outsourced intellectual property cores. As third-party involvement are more in chip design cycle, integrated circuits (IC) such as programmable logic devices (PLD) and application specific ICs (ASIC) are highly vulnerable to hardware Trojan (HT) attacks. HTs are malicious additions or modifications to existing circuit elements, which can be inserted at any stages of IC life cycle to modify/destroy the functionality, reduce reliability, leak sensitive information, etc. Besides, HT can be designed either as always on or triggered only under certain operating conditions. For example, HT attacks in safety critical applications such as nuclear power plant, space and defence will jeopardise the safety and security of the unit and cause serious consequences. Hence, it is most important to ensure that the chip being in use performs only the intended function. In this paper, an in-depth analysis of feasible HT attacks in PLD and ASIC life cycles are presented. Based on the extensive literature survey on HTs and their countermeasure techniques, the state of the art HT prevention, detection, and diagnosis techniques are recommended to the valid stages of PLD and ASIC life cycles. Therefore, incorporating possible HT defence solutions in respective phases of PLD/ASIC-based safety systems thwart them against HT attacks.

We propose a leakage power minimization approach based on multi-threshold CMOS (MTCMOS) technology. A clique partitioning-based resource allocation and binding algorithm is presented, which maximizes the idle periods of modules in the data-path. Modules with significant idle times are selectively bound to MTCMOS instances. We developed a parameterizable MTCMOS component library, characterized with respect to sleep transistor width. Using this characterization, the leakage power-delay trade-off is analyzed and optimal sleep transistor widths are identified. For three well known HLS benchmarks, we obtain an average leakage power reduction of 22.44%. The main disadvantage of MTCMOS technology is performance degradation. We present a performance recovery technique based on multi-cycling and introduction of slack. With this technique, the performance penalty reduces to as low as 14.28%. We obtain an average leakage power reduction of 17.46% after performance recovery. The average area overhead incurred due to the introduction of MTCMOS modules is 10.21%. Results are presented for 0.18 /spl mu/m CMOS technology.

The increasing complexity of instrumentation in science and industry has lead to a growth in the use of Application Specific Integrated Circuits (ASICs). Solutions using ASICs are very cost efficient in high volume production. They are also very valuable when instrument volume, functionality, and reliability are the main issues. In the standard cell approach, the ASIC designer is allowed to use predefined functional building blocks as an aid in the design process. This is advantageous when using a high-level design methodology for the digital circuits. Preverified models exist for the analogue and the digital standard cells, and thus the standard cell approach is very similar to using Field Programmable Gate Arrays (FPGAs). However, using standard cells, as opposed to full custom design techniques, leads to degraded flexibility and performance in terms of circuit density and speed. On the other hand one gains design time.

Multi-Threshold CMOS (MTCMOS) circuits combine high performance during active mode with low leakage during sleep, but have a fundamental difficulty when trying to keep the state during sleep mode. We propose several novel master-slave MTCMOS flip-flops which use an outer feedback connection in order to maintain state. These MTCMOS with Outer Feedback (MTOF) flip-flops are fast since they use only low threshold transistors on the forward (critical) path and minimum extra load. The area overhead is low since the outer feedback is simple and transistors not on the critical path can have high threshold and be reused for maintaining the state during sleep. A 100nm predictive technology with power supply ranging from 0.8V to 1.2V is used for verifying the circuits performance through simulation.

Standard cells are the most critical and reusable elements to build up the whole chip, therefore foundry has to fully qualify the standard cell libraries to ensure their high quality when releasing to the customers for the chip design. To prevent pattern dependent lithographic difficulty in manufacturing is one target of standard cell qualification and becomes mandatory especially in advanced nodes due to tighter design rules and smaller design size. To identify a lithographic problematic standard cell, we have to take its surroundings within the optical diameter range into consideration because lithographic effects are intrinsically context-dependent. One critical step is to imitate standard cells placements in real designs and consider some important factors like VIA location as it impacts the mask shape directly. When the placement is completed, lithographic simulation is performed by LFD (Litho Friendly Design) to highlight risky locations. Every standard cell has to occur enough number of times to make sure the statistics of possibility of being a problem is reliable. The final statistics will instruct engineers on how to handle the problematic standard cells, either standard cell layouts have to be optimized or building a pattern database to prevent the abutments of particular standard cell combinations.

Standard cell library is the basic for building blocks and SoC (system on chip). And design in current standard cell library always meets the most critical design rule, leading to tight lithography process window and hotspots easily. Besides, passing design rule check (DRC) cannot fully guarantee manufacturability. Lithography simulation check is an essential check item before tape out. It is significant to qualify the standard cell library at the most possible early stage in order to avoid design rework during the tape-out stage. For 14nm technology and below, hotspots appear both inside cell, abut regions of standard cells and pins for routing. Therefore, our paper puts forward a fast DFM-driven standard cell qualification approach to detect the hotspots inside cell and the potential defects from special kinds of pins and abutting standard cells. It can discover problems early and set constraints for placement and routing as early as possible for a fast product yield ramp-up.

IoT edge devices demand ultra-low leakage for lowly duty-cycled applications. It is usually believed that the static near-threshold-voltage (near-Vt) CMOS circuit is the only circuit style that is suitable for designing devices to achieve low power, low leakage, medium performance, and high robustness against PVT variations. In this work, we show that the dynamic circuit can be even better than the static circuit under the same performance requirement. First, through a design example, we obtain basic design guidelines for near-Vt dynamic circuits. Second, based on the obtained design guidelines, we demonstrate how to design a dynamic circuit with active and standby operation modes using a 32b ripple carry adder (RCA). All designs are based on 28 nm CMOS technology. We also compare the active and leakage power consumptions of both types of circuits of the same performance. For an IoT application with a 0.02% duty cycle, the 32b dynamic RCA achieves a 35% energy reduction compared to the static counterpart.