MTCMOS with outer feedback (MTOF) flip-flops

In this paper, we describe a new low-leakage standard cell based application-specific integrated circuit (ASIC) design methodology. This design is based on the use of modified standard cells, designed to reduce leakage currents (by almost two orders of magnitude) in standby mode and also allow precise estimation of leakage current. For each cell in a standard cell library, two low-leakage variants of the cell are designed. If the inputs of a cell during the standby mode of operation are such that the output has a high value, we minimize the leakage in the pull-down network, and similarly we minimize leakage in the pull-up network if the output has a low value. In this manner, two low-leakage variants of each standard cell are obtained. While technology mapping a circuit, we determine the particular variant to utilize in each instance, so as to minimize leakage of the final mapped design. We have performed experiments to compare placed-and-routed area, leakage and delays of this new methodology against Multithreshold CMOS (MTCMOS) and a regular standard cell based design style. The results show that our new methodology (which we call the "HL" methodology) has better speed and area characteristics than MTCMOS implementations. The leakage current for HL designs can be dramatically lower than the worst-case leakage of MTCMOS based designs, and two orders of magnitude lower than the leakage of traditional standard cells. An ASIC design implemented in MTCMOS would require the use of separate power and ground supplies for latches and combinational logic, while our methodology does away with such a requirement. Another advantage of our methodology is that the leakage is precisely estimable, in contrast with MTCMOS. Our primary contribution in this paper is a new low leakage design style for static CMOS designs. In addition, we also discuss techniques to reduce leakage in dynamic (domino logic) designs

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Multi Threshold CMOS (MTCMOS) circuit can be used to overcome the trade-off between speed and standby leakage current inherent in single threshold CMOS circuit. The simplest form is the dual threshold CMOS (DTCMOS), in which two threshold voltages are used in the same logic circuit. As a result, the standby power can be greatly reduced by this approach which is a key factor for battery operated devices. This paper proposed a model for analytical calculation of standby leakage current for MTCMOS Inverter circuit in 90nm technology. We have used BSIM device model which is a widely used industrial model for standby leakage current modelling of MTCMOS Inverter circuit.

Backgate biasing is a promising technique for highspeed systems. Leakage can be reduced during standby periods by reverse bias while adequate bias in active mode can balance process and temperature variations. This technique introduces no delay penalty in active mode but slow wake up time results in system performance degradation. In this paper, a backgate bias accelerator achieving 24ns/V sleep-to-active mode transition rate is demonstrated in a 90 nm CMOS technology. The circuit performs auto-calibration of the transition time as a function of the Sleep and Active mode backgate bias voltages. Those can therefore be tuned on-chip according to process variations and/or operating conditions. The accelerator occupies less than 2.5% of the total chip area, consumes 600μW during the transitions and doesn’t add any bias current during active and sleep modes.

We propose a leakage power minimization approach based on multi-threshold CMOS (MTCMOS) technology. A clique partitioning-based resource allocation and binding algorithm is presented, which maximizes the idle periods of modules in the data-path. Modules with significant idle times are selectively bound to MTCMOS instances. We developed a parameterizable MTCMOS component library, characterized with respect to sleep transistor width. Using this characterization, the leakage power-delay trade-off is analyzed and optimal sleep transistor widths are identified. For three well known HLS benchmarks, we obtain an average leakage power reduction of 22.44%. The main disadvantage of MTCMOS technology is performance degradation. We present a performance recovery technique based on multi-cycling and introduction of slack. With this technique, the performance penalty reduces to as low as 14.28%. We obtain an average leakage power reduction of 17.46% after performance recovery. The average area overhead incurred due to the introduction of MTCMOS modules is 10.21%. Results are presented for 0.18 /spl mu/m CMOS technology.

In this article, we consider a stochastic model of wireless sensor networks (WSNs) in which each sensor node randomly and alternatively stays in an active mode or a sleep mode. The active mode consists of two phases, called the full-active phase and the semi-active phase. When a referenced sensor node is in the full-active phase of the active mode, it may sense data packets, transmit the sensed packets, receive packets, and relay the received packets. However, when the phase of the sensor node switches from the full active phase to the semi-active phase, it is only able to transmit/relay data. When the referenced sensor node is in a sleep mode, it does not interact with the external world. In this article, first, we develop a stochastic model for the sensor node of a WSN, and then we derive an explicit expression of the stationary distribution of the number of data packets in the sensor node. Furthermore, we figure out some important performance measures, including the sensor node’s energy consumption for transmission, the energy consumption of the sensor operations, and the average energy consumption of the sensor node in a cycle of active and sleep modes. Also, a numerical analysis is provided to validate the proposed model and the results obtained. The novel aspects of our research are the development of a stochastic model for WSN with active and sleep features and the development of important analytical formulae for evaluating the energy consumption of a WSN. These results are expected to be useful as significant contributions to the fundamental theory of the design of various WSNs with active and sleep mode considerations.

Various high speed sequential multi-threshold voltage CMOS (MTCMOS) circuit techniques are presented and evaluated in this paper. Dedicated low leakage data preserving memory elements are integrated into the MTCMOS flip-flops. The leakage power consumption of an MTCMOS memory register is reduced by up to 67.72% as compared to the previously published conventional sequential MTCMOS circuits in a UMC 80nm CMOS technology. The control scheme required to implement a low leakage sleep mode is significantly simplified with the memory register. Furthermore, the area of the memory register is reduced by up to 46.43% as compared to the conventional MTCMOS registers.

The objective of this paper is to compare the power consumption, leakage voltage, leakage current and leakage power of 3-T DRAM while maintaining the competitive performance .The MTCOS and SVL technique is used in 3T DRAM to compare the performance. Multi-threshold CMOS(MTCMOS) is a CMOS chip which has a Transistor with multiple threshold voltage and SVL is a technique which used to reduce leakage during both the active and stand-by mode. DRAM was first invented by Dr. Robert Dennard in the year 1966. It is used in many advanced processor for chip instruction and data memory. It majorly contributes in power dissipation in off-state leakage current. In personal computers it is used as the main memory, workstations etc. The basic advantage of using DRAM is its simplicity in its structure. Keyword- DRAM; FinFET; CMOS; Leakage power; Leakage current; Frequency; Access time; MTCMOS; SVL; USVL; LSVL

This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design based on the leakage reduction mechanism. A multi-threshold logic is employed for reducing the leakage current during read/write operations. Here, the multi-threshold technique is used to insert the high threshold sleep control to the low threshold circuit. The insertion is performed in a serial manner. The high threshold transistors are very useful for deriving the low sub-threshold current. Meanwhile, the low threshold transistors are promising for improving the circuit performance. The high-low threshold transistor pairs are used to change the channel length by modifying the oxide thickness of the transistors. The overall implementation of the Multi-threshold-based SRAM cells are implemented with the help of CNFET in-order to avoid the short channel effect, mobility degradation which is occurred while considering the channel length below 32 nm in CMOS (Complementary Metal Oxide Semiconductor) devices. The paper clearly represents the performance improvement of the proposed SRAM cells with above-mentioned technologies.

Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This paper presents a tri-modal switch cell that enables implementation of multimodal power gating, including active, data-retentive drowsy, and deep sleep modes. A circuit realization and design methodology are presented that allow one to take advantage of the ultra low leakage deep sleep mode, low leakage, but very fast wakeup, drowsy mode, and an additional low leakage data-retentive mode. Experimental results demonstrate the benefits of this new switch and corresponding power gating technique.

Multi-threshold CMOS (MTCMOS) is the most widely used circuit technique for suppressing subthreshold leakage currents in idle circuits. When a conventional MTCMOS circuit transitions from SLEEP mode to ACTIVE mode, voltages of power and ground distribution networks are disturbed. Mode transition noise phenomenon in MTCMOS circuits is examined in this chapter. An MTCMOS circuit technique with three operating modes (tri-mode) is described for noise suppression during activation events. A threshold voltage tuning methodology is presented to further alleviate the mode transition noise with smaller sleep transistors in MTCMOS circuits. Alternative applications of tri-mode MTCMOS for data preservation and leakage power reduction in idle memory elements are also discussed.

The intention of this paper is to reduce leakage power and leakage current of 1-bit Full Adder while maintaining the competitive performance with few transistors are used (transistors count 10). A new high performance 1-bit Full Adder based on new logic approach is presented in this paper. MTCMOS technique which decreases the process variation on 1-bit Full Adder, the key of MTCMOS technique is applied on 1-bit Full Adder is to reduce the operating power, leakage power and leakage current. We investigate the use Multi-threshold CMOS (MTCMOS) technology provides low leakage and high performance operation by utilizing high speed, low Vth transistors for logic cells and low leakage, high Vth of transistor and show that it is particularly effective in sub threshold circuits and can eliminate performance variations with Low power. A 20 ns access time and frequency 0.05 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out 1-bit Full Adder.

Data-retention flip-flop (DRFF) efficiently maintains data during sleep mode and retains state during transitions between active and sleep mode. This paper proposes a novel source-biased stacked inverter (SBS-Inverter) and a low-leakage, structure-reused DRFF. The sleep latch circuit constructed using the SBS-Inverter can effectively reduce the power of DRFF when storing data. Reuse of the structure improves the situation of redundant transistors in certain DRFF. Fine-grained inverter level optimization reduces delay and power during the active mode. The DRFF was implemented using a 55 nm process and subjected to comprehensive analysis. Post-layout simulation results at a supply voltage of 0.4 V indicate that the proposed DRFF’s data retention leakage power is only 5.3 pW. At a supply voltage of 0.8 V, the power-delay product is only 0.146 nW*ns@20 MHz. Monte Carlo simulation results considering process, voltage and temperature (PVT) variations show that the proposed DRFF can operate reliably down to a supply voltage of 0.4 V.

Android users are occasionally troubled by the slow UI responses and sudden application/OS crashes. These problems are mainly caused by software aging, a phenomenon of progressive degradation of performance and dependability typically observed in long-running software systems. A countermeasure to software aging is software rejuvenation, i.e., manual or scheduled restart at different levels, such as application, OS, and device. Various software aging and rejuvenation models have been proposed for different software systems. However, these traditional models cannot be applied in the context of mobile devices, as they seldom consider the patterns of usage behavior and user experience specific to mobile phones. We address this problem based on the observations that the usage time of mobile phones is typically fragmented in daily life, with frequent and periodical switches between active and sleep modes, and that the user experience on fluent operation in the active mode is a key concern for mobile users. These insights are exploited to model the usage behavior and aging process by individual Stochastic Petri-Nets, and then to compose them into a Continuous Time Markov Chain (CTMC). Furthermore, we propose proactive rejuvenation strategies based on such CTMCs to achieve the best user experience and the least user interference, such as restarting the device when it is in sleep mode and before it enters an aged state. To consider user experience - a key concern of mobile users which is still less prominent in traditional dependability measurements – we propose new related metrics: for fluency (i.e., the probability that a phone offers a fast UI response to the users), and for the degree of overall user experience. We demonstrate the effectiveness and advantages of the proposed models and metrics via simulations as well as an empirical study.

Commodity HardWare (CHW) is currently used in the Internet to deploy large data centers or small computing nodes. Moreover, CHW will be also used to deploy future telecommunication networks, thanks to the adoption of the forthcoming network softwarization paradigm. In this context, CHW machines can be put in Active Mode (AM) or in Sleep Mode (SM) several times per day, based on the traffic requirements from users. However, the transitions between the power states may introduce fatigue effects, which may increase the CHW maintenance costs. In this paper, we perform a measurement campaign of a CHW machine subject to power state changes introduced by SM. Our results show that the temperature change due to power state transitions is not negligible, and that the abrupt stopping of the fans on hot components (such as the CPU) tends to spread the heat over the other components of the CHW machine. In addition, we also show that the CHW failure rate is reduced by a factor of 5 when the number of transitions between AM and SM states is more than 20 per day and the SM duration is around 800 [s].