A new architecture for area and power efficient, high conversion rate successive approximation ADCs

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

Many difficulties have confronted the system-on-chip (SoC) industry during the previous ten years. These difficulties will likely become more significant as more and more applications revolve on the Internet of Everything (IoE). These issues include reducing power consumption for greater energy efficiency, overcoming numerous causes of variation to ensure reliable performance, and reducing design area to save money and boost integration. As a result, chip designers encounter various hurdles when attempting to create stable structures with complicated angles of capability while preserving a small die size and power expenditure. Memory components are among the most critical circuit components on every chip. They account for the majority of the chip's size and power consumption, which has an impact on the overall efficacy and reliability of the chip. These consist of a diverse multitude of serial elements in logic paths, caches, register files, and large memory arrays. In contemporary synchronized CMOS circuits, sequence elements are indispensable components. In fact, they can be responsible for up to 50% of the average number of cells in a semiconductor. We propose a novel methodology aimed at enhancing the reliability of pulsed latches while ensuring that there is no substantial decline in efficiency, area, or power consumption. Furthermore, given that sequential elements can be utilized in creating compact register files, the implementation of pulsed latches in register files is reviewed and compared with other conventional implementations, including static random-access memory (SRAM) and flip-flops. Also shown are new implementations of multiport register files, which are highly beneficial for many applications. The suggested approach has been proven to considerably decrease the enormous excess in area, power consumption, and latency that is typically associated with conventional methods of designing multiport register files

VLSI computing is critical in chip fabrication in today's digital age. Moore's law demands that "the number of transistors on a microchip doubles every two years" in addition to that "the count of transistors employed in a chip size is reduced". As a result, this rule is dictating the electronics industry by reducing chip area, size, and power consumption while simultaneously enhancing chip fabrication strength. The arithmetic circuits are constructed in this work, by boosting the efficiency of circuits by considering die space as a constraint. Overall, arithmetic circuits have a bunch of usages in processing architecture. The XOR gate and multiplexer are utilized in this study to make compressor circuits more efficient by taking into account area, power, and delay. To examine the arithmetic circuit's performance, the load capacitance is customized and the power dissipation across the capacitor is studied.

Design of unbalanced ternary counters using shifting literals based D-Flip-Flops in carbon nanotube technology

Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic

Deep packet inspection (DPI) technology has conventionally been introduced for traffic monitoring, bandwidth control, bandwidth allocation, access control of specific types of traffic, etc. By installing a DPI equipment at any arbitrary point in a network, it is possible to monitor communications of many servers simply and this could simplify dramatically the conventional work load for system management and reduction of power consumption by servers. As a new potential application of DPI technology, this paper explores the possibility of applying DPI technology to server congestion control and reduction of power consumption by servers, and presents implementation examples of these applications. This paper first proposes an example of server congestion control method, in which the DPI equipment estimates the CPU usage of each server by constantly monitoring the number of live TCP connections established by each server, and moves some of virtual machines on the congested server to other servers through remote control timely. Next, this paper proposes an example of reducing power consumption by servers, in which the DPI equipment constantly monitors the traffic sent or received in each area with multiple servers. Finally, the feasibility of the proposed methods is demonstrated by an evaluation system with a real DPI equipment.

In this study, a new clock and ramp generator circuit framework with a 0.9V low operational voltage is designed for the voltage-mode/current-mode-controlled power management integrated chip of a DC-DC converter. In conventional clock and ramp generator circuit with operational amplifiers, its operational voltage is limited to be over 1.5V because of the problem of a higher threshold voltage in the metal-oxide-semiconductor field-effect transistor (MOSFET). As a result, it can not work well for a pulse-width-modulation DC-DC converter when a below 1V low-voltage single-cell clean-energy power source is applied. This newly-design clock and ramp generator circuit framework without operational amplifiers is investigated to cope with the limitation of the threshold voltage in the MOSFET. Therefore, the corresponding chip size and power consumption can be reduced. Moreover, this circuit still has the functions of adjustable clock frequency and ramp slope. In addition, numerical simulations by the HSPICE software and experimental results by a real chip fabricated in the TSMC 1P6M 0.18µm CMOS process are given to verify the effectiveness of the proposed circuit to produce the clock and ramp waveforms.

This paper describes a novel current driving circuit for an active matrix organic light emitting diode (AMOLED). The proposed current driving circuit has a lower power consumption and higher chip density for the AMOLED display compared with the conventional one because all elements operate at a normal voltage and are shielded from the high voltage of the panel. The chip size and power consumption of the current driving circuit for an AMOLED can be improved by about 30 to 40% and 10 to 20%, respectively, compared with the conventional one.

The paper presents an improved analog-to-digital converter (ADC) architecture based upon traditional successive approximation register (SAR) type ADC concepts. The most important aspect of the present design is that it resolves two or more bits in a single cycle and hence requires much lesser time than a conventional SAR ADC for conversion of same resolution. A 12-bit, 3-bit per cycle ADC logic was simulated in MATLAB SIMULINK for verification of the design. The design requires only 4 clock cycles to accomplish the conversion unlike its conventional counterpart which would require thirteen clock cycles. Seven comparators are used in parallel to resolve 3 bits during each conversion cycle. Divide and conquer algorithm is utilized here instead of the regular binary search algorithm employed for conventional SAR ADCs. Emphasis is placed on latency minimization at the cost of a nominal increase in component cost, i.e., space requirement for a particular semiconductor technology. Simulation results establish the validity of the proposed method.

Sensory search engines in a variety of applications, including DNA sequencing, are beginning to influence the way new search nanoarchitectures are constructed. This paper presents a novel nanoarchitecture based on a complementary resistive switch (CRS) construct for smart sensor search engines. Detailed operational principles of CRS, CRS-based memory array, and image matching applications using the Hamming distance measure are presented along with backing simulation results. The proposed scheme draws upon the inherent windowing behavior of fabricated CRS and hence, the duty cycle thus leading to a power dissipation of 115 nW/b, which is a reduction in power consumption by almost 50% when compared with the more conventional architectures. The variation on the match line is 100 mV/Hamming distance, providing a stable reference source for comparison input and stored data.

Objectives: Processors are computing elements of most of the embedded systems. As the technology is growing day by day, processors that are released in the market are mostly embedded processors. Processors are designed to perform concurrent operations and execution at a higher clock rate to meet the performance demands result in large heat dissipation and energy consumption. Thus there is an emphasis on power and energy consumption reduction in real time embedded processors. This work targets to reduce the processor power consumption without violating the real time constraints. Method: In this work, a dynamic power management technique named dynamic counters is employed in real-time system to minimize power consumption. The proposed method facilitates bounding of the events conservatively for effective bounding of future workload. It also employs scheduling ON and OFF time of the devices based on workload bounding at run-time. Simulation analysis is carried out to confirm the performance enhancement of the proposed method. Findings: Energy consumed by the processor increases with the number of event arrivals and switching of modes facilitates significant energy savings. Improvement: Run-time and memory overheads are overcome by dynamic counter technique. Effective bounding of future workload enhances computational efficiency.

Metal Oxide Thin Film Transistors (MO TFTs) have garnered considerable interest in emerging Internet of Things (IoT) fields such as wearable electronics, displays, Radio Frequency Identification (RFID), and biomedical monitoring, owing to their flexibility and transparency. However, limitations in channel materials make MO TFT-based circuits unipolar. Unipolar circuits often exhibit elevated short-circuit power consumption, which restricts the development of MO TFTs in the IoT sector. This paper introduces a Capacitively Coupled Near-Threshold Biasing (CCNB) technique that leverages the unique Capacitance-Voltage (C-V) characteristics of MO TFTs to bias devices in the near-threshold region, achieving nearly a 95% reduction in power consumption compared to traditional designs with the device coupling ratio (channel capacitance/overlap capacitance) at 40. Furthermore, considering the significance of clock signals in IoT applications, we have also developed a low-power full-swing Ring Oscillator (RO) based on our CCNB technique, resulting in a 90% reduction in power consumption and a nearly 70% reduction in PDP compared to conventional low-power designs.

In this article, six structures/combinations of vertical-channel-FETs (VFETs) were optimized and performance comparison with lateral-gate-all-around (LGAA) FETs and complementary FET (CFET) was made in the advanced applications across device and circuit levels. To find the main resistive and capacitive parasitic, we introduce a novel decomposition methodology for classifying key gate capacitance components. Building on these insights, we propose two optimization strategies: an inner-spacer release technique for overlap capacitance reduction in VFETs and an additional trim-etch method to mitigate resistances. The optimal gate length is also discussed considering the unique channel arrangement of VFETs. Furthermore, we presented a standard cell layout for VFETs, which was used to make direct comparisons of performance–power–area (PPA) with lateral-channel-FETs (LFETs) for 103-ring oscillator (103RO) configurations. Compared to CFET, our simulation results demonstrate that dual-channel complementary stacked VFET (dCVFET) can increase the frequency by 4.4% in iso-power and decrease power by 12.9% in iso-frequency while reducing the area by 4.1%. Compared to LGAA, dual-channel single-layer VFET (dSLVFET) achieves a 14% speed improvement or a 30.7% reduction in power consumption while also reducing the area by 20%. When adopting wrap around contact (WAC), VFETs normally outperform LFETs by achieving nearly a 16% improvement in speed or a 40% reduction in power consumption under the same area.

In this study, we consider the problem of synthesising custom networks-on-chip (NoC) architectures that are optimised for a given application. Both unicast and multicast traffic flows are considered in the input specification. We formulate the joint multicast routing and network design problem using a rip-up and reroute procedure, where each multicast routing step is formulated as a minimum directed spanning tree problem, and we propose a very efficient algorithm called Ripup-Reroute-and-Router-Merging (RRRM). Our new formulation adopts a rip-up and reroute concept that provides us with a heuristic iterative mechanism to identify increasingly improving solutions. The minimum directed spanning tree formulation efficiently captures the best routing solutions for multicast flows during the topology synthesis procedure. Our design flow integrates floorplanning, and our solutions consider deadlock-free routing. Experimental results compared with our previous proposed algorithms CLUSTER and DECOMPOSE on a variety of NoC benchmarks showed that our new synthesis results are largely improved. RRRM can on average achieve a 9% reduction in power consumption over CLUSTER and a 17% reduction in power consumption over DECOMPOSE with 1786× and 57× faster execution times than CLUSTER and DECOMPOSE, respectively. Improvements in performance were also achieved, with an average of 3% reduction in hop counts over CLUSTER and 7% in hop counts over DECOMPOSE on all benchmarks.

Most modern digital receivers sample the received RF signal at an intermediate frequency (IF), then downconvert to the baseband in the digital domain. The baseband samples are subsequently correlated with a time-limited square pulse, which is readily implemented as an integrator. Since correlation is performed at the sampling frequency, the receiver correlates at an unnecessarily high frequency. This high frequency results in significant power dissipation especially if parallel correlators are employed. By downsampling after appropriate filtering to slightly above the signal Nyquist rate, correlation is achieved at a fraction of the sampling frequency, resulting in corresponding reduction in power consumption. Furthermore, by resampling to an integer number of samples per chip, architectural changes in the correlators are possible, allowing even more reduction in power consumption. In this paper, a resampling correlator with minimal hardware overhead that outperforms the conventional correlator is presented.