A five-level zero average current error controlled single-phase grid-interactive inverter

In the present paper, single phase multilevel inverter using switched capacitor units is proposed. The switched capacitor unit (SCU) is used in the multilevel inverter will increase the dc supply voltage at the input without using transformer by operating the capacitors in parallel and in series. The SCU comprises one dc source, two semiconductor switches, power diode, and capacitor. The proposed topology does not require the charge balancing operations, which results reducing the cost of the overall circuit. In addition to that, it does not required H-bride module to alter the polarity of the output voltage, which will lead to minimum required semiconductor power switches. The proposed topology is compared with the conventional similar architectures in terms of power semiconductor switches, power diodes, dc power supplies. Finally, to confirm the proposed architecture performance, simulation results are presented.

Recently, great attention has been addressed for multilevel inverters, as they exhibit low total harmonic distortion (THD) in the output voltage and low electromagnetic interference (EMI). This paper proposes a single-phase five-level pulse width modulation (PWM) inverter for grid connection. The proposed PWM technique has some switches operated at fundamental line frequency and the others operate at inverter switching frequency. The proposed inverter has advantages of less number of components and low THD compared with the conventional multilevel inverter. The inverter operational principles and the switching functions are analyzed in this paper. Moreover, a proportional integral (PI) current control algorithm is designed and implemented in DSPACE DS1103 to keep the current injected into the grid sinusoidal and in-phase with the grid voltage for unity power factor. Simulation and experimental results prove the powerful merits of the proposed multi-level inverter and the capabilities of the proposed PWM technique.

This paper presents a single-phase multilevel inverter (MLI) with simpler basic unit cells. The proposed MLI is able to operate in two modes, i.e. charge mode to charge the batteries, and inverter mode to supply AC power to load, and therefore, it is inherently suitable for photovoltaic (PV) power generation applications. The proposed MLI requires lower number of power MOSFETs and gate driver units, which will translate into higher cost saving and better system reliability. The power MOSFETs in the basic unit cells and H-bridge module are switched at near fundamental frequency, i.e. 100 Hz and 50 Hz, respectively, resulting in lower switching losses. For low total harmonic distortion (THD) operation, a deep scanning method is employed to calculate the switching angles of the MLI. The lowest THD obtained is 8.91% at modulation index of 0.82. The performance of the proposed MLI (9-level) has been simulated and evaluated experimentally. The simulation and experimental results are in good agreement and this confirms that the proposed MLI is able to produce an AC output voltage with low THD.

The focus of this paper is a theoretical calculation of current Total Harmonic Distortion (THD) for a current source single-phase multilevel PWM inverter with CL-filter. Analytical approach to current ripple mean square / current THD calculation was introduced in the 1980s for a 2-level voltage source inverter with inductance dominated RL-load. This paper presents a generalization of this approach for a single-phase multilevel current source PWM inverter with an arbitrary number of current levels accounting for the CL-filter effect. The output of this research is a closed-form analytical current THD solution. Though one of the assumptions is large switching-to-fundamental frequencies ratio, the formulas are practically accurate for the said ratio larger than 20-25. The formulas become quite compact and simple without a loss of accuracy when using a Bessel function approximation. They demonstrate a single-phase PWM current source inverter current THD dependence on CL-filter parameters and current modulation index.

Harmonic distortion presents a significant challenge in renewable energy integration, particularly in conventional 2-level inverters. Multilevel inverters, such as the cascaded H-bridge topology, offer an effective solution by generating multiple voltage levels, thereby reducing distortion and eliminating the need for bulky filters. This study investigates harmonic reduction in a single-phase 21-level asymmetric cascaded H-bridge multilevel inverter using a novel hybrid optimization algorithm combining Artificial Bee Colony (ABC) and Firefly Algorithm (FA). The hybrid ABC-FA algorithm is designed to determine optimal switching angles for minimizing Total Harmonic Distortion (THD) while addressing the limitations of conventional heuristic methods. Modeled and simulated in MATLAB/SIMULINK, the proposed algorithm demonstrates enhanced performance in both harmonic reduction and convergence speed. Simulation results show that the hybrid ABC-FA algorithm achieves THD levels below 5%, representing a 10–20% improvement over standalone ABC or FA implementations. Additionally, the algorithm exhibits faster convergence, highlighting its effectiveness and reliability for improving power quality and facilitating efficient integration of renewable energy sources into the electrical grid.

Cascaded multilevel three-phase inverters are increasing in industries of electric drives and renewable energy because of their large capacity and suffering from high voltage shock. However, the high magnitude of common mode voltage is one of the drawbacks. Thus, the techniques of modulation and control in these multilevel inverters significantly affect the power quality of the output voltage of inverters. This paper presents a technique using fuzzy logic technique for grid-connected cascaded multilevel 3-phase inverters. This technique has completely removed the current controllers and the conventional modulation using carriers. It also helps reduce the magnitude of common mode voltage and increase the dynamic response. Moreover, the ability to reduce harmonics and switching count also helps decrease the switching loss of inverter. The simulation results on a grid-connected cascaded 5-level 3-phase inverter have validated the effectiveness of the presented technique compared with that of the conventional method using phase opposition disposition (POD) and PI current controllers.

Multilevel inverter units for stand-alone solar photovoltaic systems are gaining popularity in the present industrial environment. The number of switching devices, total harmonic distortion, number of output levels and number of sources are the governing factors in a multilevel inverter topology. The classical multilevel inverter topologies produce a considerable amount of switching losses due to handful number of switching devices as the number of output levels is increased. Therefore to overcome these drawbacks a multilevel inverter topology to maximize the number of output levels with reduced number of switching devices is opted. The staircase output voltages representing the total number of levels are obtained by the additive and subtractive combination of asymmetrically arranged voltage sources thereby reducing the total number of DC sources required. The reduction of THD and switching losses is done by selecting the suitable PWM technique with low switching frequency. Unlike in the central MPPT architecture, the distributed MPPT architecture is employed for the extraction of maximum power. A multilevel inverter for stand-alone solar PV system incorporating the features like reduced number of switches, reduced number of sources and maximizing the number of output levels with distributed MPPT architecture is designed. By this a better performance compared to the conventional methodology can be attain. The multilevel voltage source inverter with/without distributed MPPT and comparative analysis of the three types of Multicarrier Sinusoidal PWM techniques at low/high carrier wave frequency is modeled and simulation results have been taken. The simulation of the Multilevel VSI for stand-alone solar PV system is done using MATLAB R2014a software.

Cascaded H-bridge multilevel (CHBML) inverters usually include a large number of isolated dc-voltage sources. Some faults in the dc-voltage sources result in unequal cell dc voltages. Unfortunately, the conventional phase-shifted carrier (PSC) PWM method that is widely used for CHBML inverters cannot eliminate low frequency sideband harmonics when the cell dc voltages are not equal. This paper analyzes the principle of sideband harmonic elimination, and proposes an improved PSCPWM that can eliminate low frequency sideband harmonics under the condition of unequal dc voltages. In order to calculate the carrier phases, it is necessary to solve transcendental equations for low frequency sideband harmonic elimination. Therefore, an approach based on the artificial bee colony (ABC) algorithm is presented in this paper. The proposed PSCPWM method enhances the reliability of CHBML inverters. The proposed PSCPWM is not limited to CHBML inverters. It can also be applied to other types of multilevel inverters. Simulation and experimental result obtained from a prototype CHBML inverter verify the theoretical analysis and the achievements made in this paper.

Multilevel converters are very popular in medium/high power conversions due to their capability to generate high quality voltage magnitudes with low harmonics while employing devices of smaller voltage ratings. The output voltage waveform of multilevel inverter consists of multiple steppes of smaller magnitudes designed to reduce electromagnetic interference (EMI) commonly produced by rapid switching that generate lesser common mode currents at motor shaft and bearings due to reduced dv dt . The neutral point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) converters are considered as the three classical multilevel converter topologies which have found their way to industrial applications almost two decades ago. To expand the application field of multilevel converters by overcoming the challenges associated with classical topologies, new multilevel topologies and modulation techniques are developed. In this thesis, various NPC multilevel inverter topologies and its modulation techniques are investigated. Diode-clamped multilevel inverter (DCMI) for more than three-level operation is less attractive due to dc-link capacitor voltage unbalancing issues and increased conduction loses caused by the commutation of (n-1) × (n-2) clamping diodes connected in series per-leg of an n-level diode clamped inverter. A converter topology with minimum number of series connected devices which balance the total voltage equally between the semiconductors and new multilevel modulation schemes, which on more number of levels, redundant voltage vectors and zero common mode voltage vectors available in higher level DCMI, can be used together to solve the above mentioned issues. In this thesis, the voltage unbalance issues and capacitor voltage balancing techniques in DCMI are studied in detail. An extensive analysis of two modulation techniques, level-shifted PWM (LS-PWM) and space vector modulation (SVM) are presented and a SVM based voltage balancing strategy for three-level and five-level diode clamped inverters are developed by utilizing redundant switching vectors without the need of any additional controls or auxiliary circuits. The proposed balancing strategy is tested on a five-level reduced device topology. Multiple-pole multilevel diode clamped inverter (M2DCI) which is derived from three-level DCMI topology and uses lesser number of clamping diodes compared to the classic five-level DCMI. The capacitor currents as well as dc-link intermediate branch currents are obtained from the switching function model of five-level M2DCI, which reduces the number of calculations at each sampling periods while implementing the voltage balancing strategy when compared to sector based methods. The stability limits of the proposed voltage balancing strategy for M2DCI based on load power factor angle and modulation indices have been obtained at various load conditions. The investigations shown here are modeled in Matlab/Simulink® and PSIM environment and verified using experimental results. It is found that to achieve capacitor voltage balancing, modulation index is restricted to about 60% of its maximum value when loads of high power factor i.e PF ≥ 0.8 is connected at the converter terminals. Hence the proposed reduced device topology with SVM technique, which self-balances the dc-link capacitors has been extended for reactive power control in a grid connected environment. Additionally, the application of five-level multiple-pole multilevel diode-clamped converter (M2DCC) as STATic synchronous COMpensator (STATCOM) is investigated with the proposed space vector modulation based balancing strategy. The proposed scheme maintains a balanced voltage across the dc-link capacitors and exchange reactive power at various load conditions. Further, the performance of STATCOM and controllers are investigated through modelling done in Matlab/Simulink® and PSIM environment. The proposed reduced device topology together with SVM based voltage balancing technique is expected to give good performance for reactive power applications by reducing the converter losses, size, weight and THD.

Cascaded H-bridge multilevel inverter topology is one of the most popular topologies in high voltage applications. This topology uses multiple units of H-bridge power cells connected in series chain to produce AC voltage. Multilevel inverters have other topologies that can be used according to condition and demand. Pulse width modulation is a popular method to control Cascaded H-bridge inverters. This method has some disadvantages such as high power dissipation in switches when the switching frequency is high. In this paper a method called reference voltage phase disposition PWM is presented which can reduce the switching frequency. A 5 level cascaded H-bridge inverter is simulated using Matlab/Simulink and the waveforms are analyzed to illustrate effectiveness of this method. The simulation results show that without any significant changes in harmonic content, switches are relaxed and switching losses though reduced.

The hysteresis current controllers (HCC) for grid-connected inverter (GCI) system is a well-known controller for its robustness, fast reference tracking, better dynamics, and easier implementation compared to other controllers. This article proposes a modified double-band HCC (MDBHCC) for single-phase GCI system with LCL -filter. The proposed algorithm implements an unipolar symmetrical pulse width modulation (PWM) strategy for reducing inverter switching losses through a sequential logic, with an adaptive clock. It improves the variation in switching frequency and limits the maximum switching frequency of HCC while enhancing the total harmonic distortion (THD) of the injected current into the grid. In order to alleviate power quality problems, two such MDBHCC schemes, i.e., MDBHCC1 and MDBHCC2, are implemented. Where MDBHCC2 operates at the higher switching frequency with lesser % THD and MDBHCC1 operates at lower switching frequency. Simulation and experimental results are presented with a significant decrease in switching frequency and an improvement in grid current harmonics at both steady-state and dynamic conditions.

Renewable energy sources offer sustainable solutions, but the conversion of DC energy into AC energy, commonly used in electrical devices necessitates inverters. Multilevel inverters have gained favor over conventional two-level inverters in high-power, medium-voltage industrial and renewable energy applications due to their high switching frequency capabilities and ability to produce low-harmonic distortion voltage, ensuring superior power quality. This study focuses on addressing the adverse effects of harmonics in electrical systems and investigates methods to eliminate them in multilevel inverters. This study summarized current research works on traditional and advanced harmonic removal optimization strategies in multilevel inverters to highlight the limitations, objectives, THD%, and summary of existing works. Moreover, this study applies selective harmonic elimination techniques in 7-level and 15-level inverters using PSO and IPSO optimization algorithms to minimize THD and enhance inverter performance. The study summarizes current research on harmonic removal strategies in multilevel inverters, revealing the prevalent use of MATLAB/Simulink in research endeavors. Various modulation and optimization techniques have been explored to achieve low THD in the output waveform, aligning with IEEE 519 standards for power system harmonic distortion. Furthermore, the comparative analysis part highlights increasing THD improvement with higher inverter levels. The 15-level inverter stands out, achieving 6.75% THD with PSO and 4.12% with improved PSO, meeting IEEE 519's THD limit. The study underscores the importance of ongoing research in this field to advance harmonic reduction strategies, making multilevel inverters even more attractive for a wide range of applications.

We review the most common topology of multi-level inverters. As is known, the conventional inverters are utilized to create an alternating current (AC) source from a direct current (DC) source. The two-level inverter provides various output voltages [(Vdc/2) and (−Vdc/2)] of the load. It is a successive method, but it makes the harmonic distortion of the output side, Electromagnetic interference (EMI), and high dv/dt. We solve this problem by constructing the sinusoidal voltage waveform. This is achieved by a “multilevel inverter” (MLI). The multilevel inverter creates the output voltage with multiple DC voltages as inputs. Many voltage levels are combined to produce a smoother waveform. During the last decade, the multilevel inverter has become very popular in medium and high-power applications with some advantages, such as the reduced power dissipation of switching elements, low harmonics, and low EMIs. We introduce the information about several multilevel inverters such as the diode-clamped multilevel inverter (DC-MLI), cascaded H-bridge multilevel inverter (CHB-MLI), and flying-capacitor multilevel inverter (FC-MLI) with Power systems CAD (PSCAD) simulation. It is shown that THD is 28.88% in three level FC-MLI while THD is 18.56% in five level topology. Therefore, we can decrease the total harmonic distortion adopting the higher-level topology.

Reduced voltage stress across switches, stepped waveform and better harmonic profile make multilevel inverter a better choice over traditional inverter. However, the number of switches and other associated elements increase with the number of levels at the output voltage and results in increased size, cost and complexity. Many new inverter structures have been developed and modified to improve the level to switch ratio (LSR). This paper proposes one such improved single phase inverter topology. The proposed structure is corroborated by formulating a nine-level inverter. Further, the proposed structure is compared with the traditional asymmetric structure in terms of LSR.

A Generalized WECS System with Single Phase Multilevel Inverter having MPPT control with Neural Network