Reduction of common mode voltage for grid-connected multilevel inverters using fuzzy logic controller

Introduction. The advantages of a high-power quality waveform and a high voltage capability of multilevel inverters have made them increasingly popular in recent years. These inverters reduce harmonic distortion and improve the voltage output. Realistically speaking, as the number of voltage levels increases, so does the quality of the multilevel output-voltage waveform. When it comes to industrial power converters, these inverters are by far the most critical. Novelty. Multilevel cascade inverters can be used to convert multiple direct current sources into one direct current. These inverters have been getting a lot of attention recently for high-power applications. A cascade H-bridge multilevel inverter controller is proposed in this paper. A change in the pulse width of selective pulse width modulation modulates the output of the multilevel cascade inverter. Purpose. The total harmonic distortion can be reduced by using filters on controllers like PI and fuzzy logic controllers. Methods. The proposed topology is implemented with MATLAB/Simulink, using gating pulses and pulse width modulation methodology and fuzzy logic controllers. Moreover, the proposed model also has been validated and compared to the hardware system. Results. Total harmonic distortion, number of power switches, output voltage and number of DC sources are analyzed with conventional topologies. Practical value. The proposed topology has been very supportive for implementing photovoltaic based multilevel inverter, which is connected to large demand in grid and industry.

Multilevel converters are very popular in medium/high power conversions due to their capability to generate high quality voltage magnitudes with low harmonics while employing devices of smaller voltage ratings. The output voltage waveform of multilevel inverter consists of multiple steppes of smaller magnitudes designed to reduce electromagnetic interference (EMI) commonly produced by rapid switching that generate lesser common mode currents at motor shaft and bearings due to reduced dv dt . The neutral point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) converters are considered as the three classical multilevel converter topologies which have found their way to industrial applications almost two decades ago. To expand the application field of multilevel converters by overcoming the challenges associated with classical topologies, new multilevel topologies and modulation techniques are developed. In this thesis, various NPC multilevel inverter topologies and its modulation techniques are investigated. Diode-clamped multilevel inverter (DCMI) for more than three-level operation is less attractive due to dc-link capacitor voltage unbalancing issues and increased conduction loses caused by the commutation of (n-1) × (n-2) clamping diodes connected in series per-leg of an n-level diode clamped inverter. A converter topology with minimum number of series connected devices which balance the total voltage equally between the semiconductors and new multilevel modulation schemes, which on more number of levels, redundant voltage vectors and zero common mode voltage vectors available in higher level DCMI, can be used together to solve the above mentioned issues. In this thesis, the voltage unbalance issues and capacitor voltage balancing techniques in DCMI are studied in detail. An extensive analysis of two modulation techniques, level-shifted PWM (LS-PWM) and space vector modulation (SVM) are presented and a SVM based voltage balancing strategy for three-level and five-level diode clamped inverters are developed by utilizing redundant switching vectors without the need of any additional controls or auxiliary circuits. The proposed balancing strategy is tested on a five-level reduced device topology. Multiple-pole multilevel diode clamped inverter (M2DCI) which is derived from three-level DCMI topology and uses lesser number of clamping diodes compared to the classic five-level DCMI. The capacitor currents as well as dc-link intermediate branch currents are obtained from the switching function model of five-level M2DCI, which reduces the number of calculations at each sampling periods while implementing the voltage balancing strategy when compared to sector based methods. The stability limits of the proposed voltage balancing strategy for M2DCI based on load power factor angle and modulation indices have been obtained at various load conditions. The investigations shown here are modeled in Matlab/Simulink® and PSIM environment and verified using experimental results. It is found that to achieve capacitor voltage balancing, modulation index is restricted to about 60% of its maximum value when loads of high power factor i.e PF ≥ 0.8 is connected at the converter terminals. Hence the proposed reduced device topology with SVM technique, which self-balances the dc-link capacitors has been extended for reactive power control in a grid connected environment. Additionally, the application of five-level multiple-pole multilevel diode-clamped converter (M2DCC) as STATic synchronous COMpensator (STATCOM) is investigated with the proposed space vector modulation based balancing strategy. The proposed scheme maintains a balanced voltage across the dc-link capacitors and exchange reactive power at various load conditions. Further, the performance of STATCOM and controllers are investigated through modelling done in Matlab/Simulink® and PSIM environment. The proposed reduced device topology together with SVM based voltage balancing technique is expected to give good performance for reactive power applications by reducing the converter losses, size, weight and THD.

The current work proposes a novel design of Cascaded H-bridge (CHB) and half-bridge for an asymmetric hybrid Multi-Level Inverter (MLI) to generate a nine-level output using a reduced number of power switches. By utilizing three unequal DC voltage sources, the proposed topology achieves an extended range of nine-level output voltages while maintaining a simplified and compact architecture. A comprehensive evaluation of the proposed asymmetric MLI was conducted, namely, the cost function, component count per level, and total standing voltage. The output performance of the proposed MLI was evaluated using three carrier-based Pulse Width Modulation (PWM) techniques: Phase Disposition (PD), Phase Opposition Disposition (POD), and Alternate Phase Opposition Disposition (APOD), and by simulating in MATLAB Simulink a Photovoltaic (PV) system under variable irradiance. The simulation results revealed that the PD technique demonstrated superior performance in achieving the lowest Total Harmonic Distortion (THD) of 13.98% at a modulation index of 0.95. A comparative analysis was performed with other existing topologies. The proposed topology achieved a Total Standing Voltage per unit (TSVPU) of 18 VDC and cost function values of 4.75 and 6.25, while the total component count per level was calculated as 1.67, which is comparatively lower than that of the existing topologies. In conclusion, the reduction of the switch count significantly decreases the switching losses, system complexity, and installation costs compared to traditional MLI configurations.

Cascaded multilevel three-phase inverters are commonly used in industrial applications and the quality of these inverters is highly dependent on the modulation techniques. The common mode voltage is one of the factors affecting the quality of the three-phase inverter output voltage. This paper proposes a carrier phase modulation method for cascade multilevel inverters to reduce the magnitude of common-mode voltage magnitude and harmonics. In the proposed method, the carrier phase modulator is considered as an adaptive controller and the phase of carrier is completely controlled by the magnitude of control signal. The phase modulation has a high immunity to the noises compared with the modulations of frequency and amplitude because it is difficult for noises to intrude into the phase of carrier. In addition, the algorithm of carrier phase modulation is simple and requires little memory. Moreover, the number of switching commutations of the proposed method also reduces significantly. Simulation and experiment results based on a cascaded five-level three-phase inverter system have confirmed the effectiveness of the proposed method compared with that of the popular methods using unmodulated carriers such as phase disposition (PD) and phase opposite disposition (POD).

In this chapter, different multilevel level inverters, which have been presented in the literature, were studied. These studies included the calculation of the key equations that can be considered as the characteristics of topology, such as the count of the switches, IGBTs, DC voltage sources, the variety in the magnitudes of the DC voltage sources, the total blocked voltage by the switches, and the maximum count of switches that are switched on to pass the output current. In the end, a comparative study was done using some of these topologies to determine the advantages and demerits of these topologies toward the conventional H-bridge inverter. The results of these comparisons were studied, and it has resulted that some of these topologies show better features in some parameters. However, they may show worse results in the other parameters. Moreover, the meaning of optimization in multilevel inverters was described and applied to a multilevel inverter topology.

This paper deals about fuzzy logic control of closed loop controlled five level Multi Level Inverter (MLI) driven three phase induction motor. Three phase Induction motor is most widely used drive in Industries, so needs proper control of speed. Induction motor is fed from five level multilevel inverter which is controlled by fuzzy logic. The closed loop consists of two loops. First inner loop is current loop and second outer loop is speed loop. The torque is varied at different times and corresponding change in speed and Total Harmonic Distortion (THD) is observed. The MLI is controlled by Sinusoidal Pulse Width Modulation (SPWM) Technique. DOI: http://dx.doi.org/10.11591/ijpeds.v3i2.3062

Abstract: The conventional two-level inverter is most commonly used for AC drive systems. The inverter produces harmonics, which will cause heating of the power electronic devices as well as load and deteriorate the life of it. Thus, anyhow harmonics should be suppressed or removed, the most common or well-known method to filter out harmonics are introduction of various filters between inverter and load according to requirements. The filters are mainly designed with L and C connection in different ways, the use of filters become more bulky and costly. To design accurate desired response filters are complex. These issues of filters for the high voltage ratings and higher power applications can be solved by multilevel (ML) inverters topology. In this paper cascaded 5-level and 7-level single phase inverter is being compared with conventional 2-level single phase inverter through proposed simulation model. MLI using cascaded H-Bridge is more advantageous than conventional 2-level such as reduced dv/dt stress improves the EMC problem. Multilevel inverters are more reliable than two-level inverters at lower speed. Voltage rating of each cell in cascaded H-Bridge inverter topology are of low values to obtain 230 AC output MLI is mostly used for stored power in batteries and fuel cell. The inverter can generate different level stepped staircase output voltages at load side to produce more sinusoidal voltage signals and to reduce the THD value. THD value of MLI using cascaded H-Bridge topology reduces on increasing number of levels. Keywords: Total harmonic distortion (THD), electromagnetic compatibility (EMC), and multilevel inverter (MLI) Cite this Article Vijay Shankar, Ankur Kumar, A.N. Tiwari. Harmonics Analysis of Single Phase VSI with 5-level and 7-level Inverter. Recent Trends in Electronics & Communication Systems. 2019; 6(1): 16–23p.

In this paper, a direction to reduce common-mode voltage (CMV) at the output of multilevel inverters (MLI) using a sinusoidal pulse width modulation (SPWM) technique is discuss. As SPWM technique does not require computations therefore, it is easy to implement in digital controllers. This paper makes the simulation implementation of a SPWM technique to reduce CMV using a three-level inverter for a three phase RL-load. Simulation results shows and explain the feasibility of the proposed technique.

This paper, give solution to reduce Common-Mode Voltage (CMV) at the output of motor drive using a Sinusoidal Pulse Width Modulation (SPWM) technique. As SPWM doesn't require computations therefore, it can be implement in digital controllers. This paper shows simulation and hardware implementation of a SPWM technique to reduce CMV using a three-level inverter for a three phase motor load. The gate pulses for the inverter are generated by using microcontroller dsPIC33EP256MU810. A simulation and hardware result shows and explain the practicability of the technique.

Recently multilevel inverters (MLIs) have received wide attention from industry and academia, as they are changing into a viable technology for diverse applications. To produce high-quality output using less switch count, development of novel reduced switch MLI (RS MLI) topologies has been a focus of current research theme. This paper presents design and control of a switched-diode dual source single switch MLI (SDDS MLI). The generalized SDDS MLI is first designed using an asymmetric basic unit. Proposed SDDS MLI requires less switch count and driver circuit count compared with the few recently developed RS MLI topologies. To improve the voltage quality by eliminating targeted low-order harmonics, a modified version of fish swarm optimization algorithm is examined for computing optimum switching angles required to control the SDDS MLI. Moreover, suitability and superiority of the derived algorithm are established by comparing with traditional selective harmonic elimination techniques. The developed topology is investigated through several MATLAB simulations as well as experimental tests in the laboratory applying the modified control approach.

This paper proposes a grid-connected Photovoltaic (PV) system based on a multilevel Current Source Inverter (CSI) topology. The topology proposed here consists of parallel-connected CSI modules operating at a very low switching frequency. For n number of inverter modules, 2n+1 current levels are resulted in the output. In the multilevel inverter topology, each inverter module has its own PV source, Maximum Power Point Tracking (MPPT) unit, and DC-link current controller. Unlike earlier proposed multilevel CSI topologies, the proposed topology has a single AC-side current controllers, lowering the requirements for AC-side sensors and filters. To demonstrate the performance of the multilevel inverter based on CSI, two inverter units are considered in this study. The simulation studies are carried out in PSCAD/EMTDC environment.

<p>The popularity of multilevel inverters have increasing over the years in various applications without use of a transformer and has many benefits. This work presents the performance and comparative analysis of single phase diode clamped multilevel inverter and a hybrid inverter with reduced number of components. As there are some drawbacks of diode clamped multilevel inverter such as requiring higher number of components, PWM control method is complex and capacitor voltage balancing problem, an implementation of hybrid inverter that requires fewer components and less carrier signals when compared to conventional multilevel inverters is discussed. The performance of single phase diode clamped multilevel inverter and hybrid multilevel inverter for seven, nine and eleven levels is performed using phase disposition, alternate phase opposition disposition sinusoidal pulse width modulation techniques. Both the multilevel inverter are implemented for the above mentioned multicarrier based Pulse Width Modulation methods for R and R-L loads. The total harmonic distortion is evaluated at various modulation indices. The analysis of the multilevel inverters is done by simulation in matlab / simulink environment.</p>

Three-level inverter has been widely used in electric drives and renewable power generation system. However, the common mode voltage (CMV) and output current ripple reduction of three-level inverter should be carefully regulated for the appropriate operation. As these two targets are mutually interrelated, the conventional space vector modulation (SVM) scheme cannot cope with them decently. To overcome this drawback, this paper proposes a novel modified SVM scheme to realize CMV and current ripple reduction simultaneously. The generating mechanism of output current ripple is analyzed, and the relationship between current ripple and utilized vectors is quantitatively described. Based on the analyses, the proposed optimal current ripple and CMV reduction pulse width modulation (OCR-CMVRPWM) method adopts four voltage vectors (large, medium, small and zero vectors) to reduce root mean square (RMS) value of current ripple by allocating the sequence and dwell times of utilized vectors. Compared to the existing PWM methods, the proposed OCR-CMVRPWM scheme can reduce the peak of CMV to half of value using the conventional SVM, and obtain a significant reduction of output current total harmonic distortion (THD). The effectiveness of the proposed method is validated by both simulation and experimental results.

Multilevel inverters are gaining popularity in high power applications. This paper proposes a new ladder type structure of cascaded three-phase multilevel inverter with reduced number of power semiconductor devices which is used to drive the induction motor. The ultimate aim of the paper is to produce multiple output levels with minimum number of semiconductor devices. This paper uses only 11 switches along with 3 diodes and 4 asymmetrical sources to produce an output voltage of 21 levels. The modulation technique plays a major role in commutation of the switches. Here we implement the multicarrier level shifting pulse width modulation technique to produce the commutation signals for the inverter. The proposed multilevel inverter is used to drive the three-phase induction motor. The mathematical modeling of three-phase induction motor is done using Simulink. Furthermore the PI and fuzzy logic controllers are also used to produce the reference waveform of the level shifting technique which in turn produces the commutation signals of the proposed multilevel converter. The controllers are used to control the speed of the induction motor. The effectiveness of the proposed system is proved with the help of simulation. The simulation is performed in MATLAB/Simulink. From the simulation results, it shows that the proposed multilevel inverter works properly to generate the multilevel output waveform with minimum number of semiconductor devices. The PI and fuzzy logic controller performances are evaluated using the results which indicate that with the help of controllers the harmonics has been reduced and the speed control of induction motor is achieved under different loading conditions.

The performance analysis of modified multilevel DC link inverter (MMLDCLI) operating with various carrier‐based pulse width modulation (CB‐PWM) techniques is studied. In MMLDCLI, seven‐level is achieved with six controllable switches only, making it an attractive option as a reduced device count multilevel (MLI, multilevel inverter) topology. MMLDCLI operates with two different levels of voltage source, and the absence of transformer makes this topology suitable for photovoltaic (PV) applications. Two different levels of sources can be achieved with two different combinations of PV panel arrangements. The CB‐PWM is reputed modulation approach for MLIs. In this study, various CB‐PWM techniques are implemented for MMLDCLI to evaluate performance parameters such as harmonic analysis, device losses and device stress. All the simulations are performed in SIMULINK, and hardware prototype is developed to validate the results.