A Fixed-point 3D Graphics Library with Energy-efficient Cache Architecture for Mobile Multimedia Systems

Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. The performance of a given cache architecture is largely determined by the behavior of the application using that cache. Desktop systems have to accommodate a very wide range of applications and therefore the manufacturer usually sets the cache architecture as a compromise given current applications, technology and cost. Unlike desktop systems, embedded systems are designed to run a small range of well-defined applications. In this context, a cache architecture that is tuned for that narrow range of applications can have both increased performance as well as lower energy consumption. We introduce a novel cache architecture intended for embedded microprocessor platforms. The cache can be configured by software to be direct-mapped, two-way, or four-way set associative, using a technique we call way concatenation, having very little size or performance overhead. We show that the proposed cache architecture reduces energy caused by dynamic power compared to a way-shutdown cache. Furthermore, we extend the cache architecture to also support a way shutdown method designed to reduce the energy from static power that is increasing in importance in newer CMOS technologies. Our study of 23 programs drawn from Powerstone, MediaBench and Spec2000 show that tuning the cache's configuration saves energy for every program compared to conventional four-way set-associative as well as direct mapped caches, with average savings of 40% compared to a four-way conventional cache.

A deterministic way-prediction scheme using power-aware replacement policy

Article Free Access Share on Way-predicting set-associative cache for high performance and low energy consumption Authors: Koji Inoue Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPAN Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPANView Profile , Tohru Ishihara Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPAN Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPANView Profile , Kazuaki Murakami Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPAN Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPANView Profile Authors Info & Claims ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and designAugust 1999 Pages 273–275https://doi.org/10.1145/313817.313948Online:17 August 1999Publication History 216citation1,327DownloadsMetricsTotal Citations216Total Downloads1,327Last 12 Months55Last 6 weeks15 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Multi-core processors are increasingly popular because they yield higher performance, but they also present new challenges for hard real-time systems in that they make it much more difficult to estimate a task's worst-case execution time (WCET). Partitioned cache architecture is being used to ease the problem by providing an isolated execution environment for each thread. Although simple to implement and use, this method may be sub-optimal with respect to both energy consumption and performance since it prevents taking advantage of information shared across threads for both instructions and data. This work presents a new cache architecture termed SPACE (Semi-Partitioned CachE) that makes it possible to leverage information sharing, yielding in turn a tighter WCET. The SPACE architecture together with our new WCET algorithm can be used to maintain the predictability of the execution time of the parallel threads while reducing the overall energy consumption of the system. The new proposed cache architecture was implemented using Verilog and deployed on a Xilinx MicroBlaze multi-core design for testing, validation and measurements. The application level experiments were conducted using the Chronos tool for estimation and the Wattch/SimpleScalar simulator for execution. Using three real-time programs–a radar tracker, a DES encryption algorithm, and an FM radio–we showed that SPACE together with the enhanced WCET algorithm reduce the average system WCET of these applications by 31 percent and reduce the actual energy consumption by 18 percent in comparison with other cache architectures.

A reconfigurable cache architecture for object-oriented application-specific instruction set processors (ASIP) is presented in this paper. The embedded ASIPs we follow in this research are specifically designed to suit object-oriented applications and are synthesized form an object-oriented high-level specification. The ASIPs are composed of a processor core along with a number of hardware functional units. In order to support concurrent execution of the functional units, we propose a cache architecture which is virtually divided into a number of partitions. The partition sizes can be dynamically changed depending on the run-time behavior of the application. Partitioning the cache not only provides the concurrent memory access for the functional units, but also reduces the number of tag comparisons per cache access. We also develop a simple and energy-efficient cache consistency mechanism among cache partitions. In this paper we evaluate the impact of the proposed cache architecture on the cache energy consumption, by implementing it in a number of our ASIPs. The results show that the proposed cache architecture reduces the number of tag comparisons per cache access by 39% on average

In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set-associative cache for low energy consumption while maintaining performance. The proposed architecture accesses each way in sequence, and then eliminates subsequent accesses if a hit is detected. It features smart cache placement and replacement policies to minimize the number of required access cycles. It can also reduce the heavy fanout load of the hit-signal, which suppresses the possible increase of cache cycle time due to more complicated cache control mechanism. The experimental results show that a 32 KB 2-way sequential way-access set-associative cache reduces the energy consumption by 24% compared against a conventional 2-way set-associative cache with the same size at virtually no performance loss.

In this paper, we describe the Iris recognition system based on 32-bit floating point digital signal processor (DSP) and 32-bit advanced RISC machines(ARM). Iris recognition is more accurate and stability compare to other biometric recognition techniques and it is also a remote recognition using machine vision, meanwhile it is a biometric recognition technique without invasion.This paper design an embedded iris recognition system base on ARM and DSP. The system has integrated with image acquisition, image process, image recognition and has advantages of high speed, small size, low power requirement and etc.

In this paper, we focus on low power design at the architecture level and propose a new architecture, called sentry tag, for reducing the on-chip cache power consumption in processors. The many unnecessary activities in the conventional cache-access process motivate our proposal. By pre-comparing the sentry bit of the access address with the sentry tag before starting a normal cache access, we can filter out and eliminate most unnecessary activities. Thus the power consumption can be effectively reduced. Our method is valuable for both a conventional cache with parallel access and a phased cache with serial access. We used SimpleScalar, a trace-driven simulator, to evaluate the performance of our proposed architecture. Compared to a conventional cache, experimental results from SPEC95 benchmarks show that the additional sentry tag can reduce many unnecessary activities (and hence the power consumption), while the hardware overhead is insignificant. For example, an 8-KB, 4-way data cache with two-bit sentry tag can improve the power consumption by 35% compared to a conventional set-associative cache. The maximum power saving achieved using this architecture depends on the cache configuration, which suggests that the proposed sentry tag is a viable choice for data caches with higher associativity.

Many tools have been developed to visualize protein and molecular structures. Most high quality protein visualization tools use the OpenGL graphics library as a 3D graphics system. Currently, the performance of recent 3D graphics hardware has rapidly improved. Recent high-performance 3D graphics hardware support Microsoft Direct3D graphics library more than OpenGL and have become very popular in personal computers (PCs). In this paper, a molecular visualization system termed ProteinVista is proposed. ProteinVista is well-designed visualization system using the Microsoft Direct3D graphics library. It provides various visualization styles such as the wireframe, stick, ball and stick, space fill, ribbon, and surface model styles, in addition to display options for 3D visualization. As ProteinVista is optimized for recent 3D graphics hardware platforms and because it uses a geometry instancing technique, its rendering speed is 2.7 times faster compared to other visualization tools.

With the rapid growth of big data information and the continuous iteration progress of CPU architecture, the implementation of a new memory-based cache architecture is urgent and challenging. In the paper, a CPU cache architecture system based on MRAM is built. Firstly, the performance of SRAM, STT-MRAM and SOT-MRAM as caches from 8 kb to 32 Mb is evaluated. Secondly, by summarizing the performance of SRAM and MRAM in different cache levels, a new quad-core CPU cache architecture design scheme with SOT-MRAM as the first level of cache and STT-MRAM as the second level of cache is determined. Thirdly, the built cache system is simulated. A non-inclusive strategy is proposed to replace the inclusive strategy in order to solve the problem of high dynamic energy of STT-MRAM at the second level. The idea of having a quad-core CPU dynamically share the second-level cache is proposed in the paper. Finally, the caching system in the paper is compared with the other previous works, showing up to 60.78% energy consumption advantage and 33.22% leakage power advantage. The proposed MRAM-based CPU cache system and the corresponding cache strategy have potential application with the benefits of low power and less area.

Effect of high-pressure grinding rolls pretreatment on the preparation of vanadium-titanium magnetite pellets

Membrane desalination and water re-use for agriculture: State of the art and future outlook

Many authors have proposed power management techniques for general-purpose processors at the cost of degraded performance such as lower IPC or longer delay. Some proposals have focused on cache memories because they consume a significant fraction of total microprocessor power. We propose a reconfigurable and adaptive cache microarchitecture based on field-programmable technology that is intended to deliver high performance at low energy consumption. In this paper, we evaluate the performance and energy consumption of a run-time algorithm when used to manage a field-programmable L1 data cache. The adaptation strategy is based on two techniques: a learning process provides the best cache configuration for each program phase, and a recognition process detects program phase changes by using data working-set signatures to activate a low-overhead reconfiguration mechanism. Our proposals achieve performance improvement and cache energy saving at the same time. Considering a design scenario driven by performance constraints, we show that processor execution time and cache energy consumption can be reduced on average by 15.2% and 9.9% compared to a non-adaptive high-performance microarchitecture. Alternatively, when energy saving is prioritized and considering a non-adaptive energy-efficient microarchitecture as baseline, cache energy and processor execution time are reduced on average by 46.7% and 9.4% respectively. In addition to comparing to conventional microarchitectures, we show that the proposed microarchitecture achieves better performance and more cache energy reduction than other configurable caches.

With the development of the micro-electronics and computer technology, especially with the expansion of field programmable gate array (FPGA), the reconfigurable system technology is becoming the key issue of research and application. In this paper, the principle of the dynamically reconfigurable FPGA, the method and flow of the configurable design are introduced. Based on the application requirement of the modular reconfigurable robot (MRR), a designing method of reconfigurable robot controller is proposed, which is based on the Advanced RISC Machine (ARM) processor and FPGA. The design principle, internal logic function design and the design course of the reconfiguration method are presented. Finally, the experiments of the MRR prove the feasibility of the reconfigurable robot controller to different configuration requirement of MRR and the efficiency of the software and hardware resource.

Current interest in self-timed systems is motivated by the area, power and design effort required for the global clock of VLSI synchronous designs. A self-timed data-path, based on the ARM (Advanced RISC Machine) processor, using 'micropipeline' control techniques has been developed for a newly updated high-performance differential bipolar technology. This paper describes the architectural model produced to verify the correctness of the prototype design, and the use of the model in evaluating and enhancing the processor performance. Self-timed design comprises independent blocks whose operation depends solely on input data and unit availability. The modelling of the dynamic behaviour of blocks and the control structures required are presented. These illustrate how easily and well the self-timed operation is mapped onto the Verilog modelling language. Benchmark results on the processor indicate a factor-of-two performance improvement over a CMOS version. The system state at a particular instant is difficult to determine and the effects of interactions between modules are difficult to quantify. The use of the model to explore design changes, particularly to the buffering structures, is presented. This allows the design to be 'tuned' to the technology. It also enables a better understanding of total system behaviour.