A highly configurable cache architecture for embedded systems

A 3D computer graphics (3DCG) library with energy-efficient cache architecture is implemented for mobile multimedia systems. The developed library is based on fixed-point arithmetic for low energy consumption. To achieve high performance, the library is optimized at both the assembly and the algorithm levels on 3 different advanced RISC machine (ARM) processors. In order to enhance energy-efficiency as well as performance, a series of simulations have been performed on application programs with various cache configurations. We find that a 2-way set associative cache consumes low energy with negligible performance degradation. In this cache system, the optimized library can achieve 66.1% performance improvement and 25.3% energy saving on average compared with the conventional 4-way set associative cache system. Software and hardware co-optimization achieves 67 K polygons/s with low energy consumption. We verified the graphics library with proposed cache architecture by implementing a mobile graphics LSI.

Multi-core processors are increasingly popular because they yield higher performance, but they also present new challenges for hard real-time systems in that they make it much more difficult to estimate a task's worst-case execution time (WCET). Partitioned cache architecture is being used to ease the problem by providing an isolated execution environment for each thread. Although simple to implement and use, this method may be sub-optimal with respect to both energy consumption and performance since it prevents taking advantage of information shared across threads for both instructions and data. This work presents a new cache architecture termed SPACE (Semi-Partitioned CachE) that makes it possible to leverage information sharing, yielding in turn a tighter WCET. The SPACE architecture together with our new WCET algorithm can be used to maintain the predictability of the execution time of the parallel threads while reducing the overall energy consumption of the system. The new proposed cache architecture was implemented using Verilog and deployed on a Xilinx MicroBlaze multi-core design for testing, validation and measurements. The application level experiments were conducted using the Chronos tool for estimation and the Wattch/SimpleScalar simulator for execution. Using three real-time programs–a radar tracker, a DES encryption algorithm, and an FM radio–we showed that SPACE together with the enhanced WCET algorithm reduce the average system WCET of these applications by 31 percent and reduce the actual energy consumption by 18 percent in comparison with other cache architectures.

Present complementary metal–oxide–semiconductor (CMOS) technology with scaled channel lengths exhibits higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier-based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption, with increased vulnerability. Additionally, spin-transfer torque magnetic tunnel junction (STT-MTJ) and CMOS-based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of the STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel field effect transistor (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET-based sense amplifier-based logic (SABL) gates are proposed that achieve 3× lower energy consumption than the Si FinFET SABL designs. Further, utilizing TFET SABL gates, a TFET PRIDE S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption than the FinFET designs. With the resulting lower static power consumption, TFET SABL-based cryptosystems are thus less vulnerable to static power side-channel attacks. Additionally, the proposed STT-MTJ and TFET LiM gates achieve 4× lower energy consumption than the STT-MTJ and FinFET designs. Lastly, these gates are explored in a logic encryption/locking technique that shows 3.1× lower energy consumption than the STT-MTJ and FinFET-based design.

The probability of timing failure in SRAM accessing becomes unacceptably high at low voltages, which makes the SRAM become the bottleneck of the system performance. Recently proposed timing speculation SRAM (SSRAM) can access bit cells much earlier than the conservative time margin and detect the potential timing failures. Unfortunately, the performance benefit brought by this speculative scheme might be nullified by the extra cycles used to correct the errors. Therefore, in a cache architecture, cachelines containing bit cells with timing failure bring significant performance degradation in a low-voltage scenario. In this paper, we propose the set-associative L1 and L2 Remapping and Reuse-aware timing Speculation caches (RRS caches) based on the cross-sensing SSRAM to reduce the weak cacheline access penalties under low supply voltages. RRS caches improve the proportion of the error-free cachelines (or strong cachelines) by clustering as more as possible bit cells with timing failures into weak cachelines. In addition, RRS caches swap the frequently reused data to the error-free cachelines to further reduce the average access latency and the energy consumption by an optimized filling/replacement policy. We compared the performance, energy consumption and area overhead of RRS caches with those of state-of-the-art approaches. According to our simulation results, RRS caches improve the system performance close to that of the Perfect caches in a four-core processor with only 0.12% extra energy consumption, 4.12% extra area overhead in the L1 cache and 2.69% extra energy consumption, 5.66% extra area overhead in the L2 cache compared to the cache designs with the raw SSRAM.

The instruction cache is a critical component in any microprocessor. It must have high performance to enable fetching of instructions on every cycle. However, current designs waste a large amount of energy on each access as tags and data banks from all cache ways are consulted in parallel to fetch the correct instructions as quickly as possible. Existing approaches to reduce this overhead remove unnecessary accesses to the data banks or to the ways that are not likely to hit. However, tag hunks still need to be checked. This paper considers a new hybrid hardware and linker-assisted approach to tagless instruction caching. Our novel cache architecture, supported by the compilation toolchain, removes the need for tag checks entirely for the majority of cache accesses. The linker places frequently-executed instructions in specific program regions that are then mapped into the cache without the need for tag checks. This requires minor hardware modifications, no ISA changes and works across cache configurations. Our approach keeps the software and hardware independent, resulting in both backward and forward compatibility. evaluation on a superscalar processor with and without SMI' support shows power savings of 66% within the instruction cache with no loss of performance. This translates to a 49% saving when considering the combined power of the instruction cache and translation lookaside buffer, which is involved in managing our tagless scheme.

Many authors have proposed power management techniques for general-purpose processors at the cost of degraded performance such as lower IPC or longer delay. Some proposals have focused on cache memories because they consume a significant fraction of total microprocessor power. We propose a reconfigurable and adaptive cache microarchitecture based on field-programmable technology that is intended to deliver high performance at low energy consumption. In this paper, we evaluate the performance and energy consumption of a run-time algorithm when used to manage a field-programmable L1 data cache. The adaptation strategy is based on two techniques: a learning process provides the best cache configuration for each program phase, and a recognition process detects program phase changes by using data working-set signatures to activate a low-overhead reconfiguration mechanism. Our proposals achieve performance improvement and cache energy saving at the same time. Considering a design scenario driven by performance constraints, we show that processor execution time and cache energy consumption can be reduced on average by 15.2% and 9.9% compared to a non-adaptive high-performance microarchitecture. Alternatively, when energy saving is prioritized and considering a non-adaptive energy-efficient microarchitecture as baseline, cache energy and processor execution time are reduced on average by 46.7% and 9.4% respectively. In addition to comparing to conventional microarchitectures, we show that the proposed microarchitecture achieves better performance and more cache energy reduction than other configurable caches.

Comparison of energy consumption and specific energy requirements of different methods for drying mushroom slices

Memory accesses often account for about half of a microprocessor system's power consumption. Customizing a microprocessor cache's total size, line size, and associativity to a particular program is well known to have tremendous benefits for performance and power. Customizing caches has until recently been restricted to core-based flows, in which a new chip will be fabricated. However, several configurable cache architectures have been proposed recently for use in prefabricated microprocessor platforms. Tuning those caches to a program is still, however, a cumbersome task left for designers, assisted in part by recent computer-aided design (CAD) tuning aids. We propose to move that CAD on-chip, which can greatly increase the acceptance of tunable caches. We introduce on-chip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune the cache to an executing program. Our heuristic seeks not only to reduce the number of configurations that must be examined, but also traverses the search space in a way that minimizes costly cache flushes. By simulating numerous Powerstone and MediaBench benchmarks, we show that such a dynamic self-tuning cache saves on average 40% of total memory access energy over a standard nontuned reference cache.

In this chapter a novel fault tolerant cache architecture named Resizable Data Composer-Cache (RDC-Cache) is introduced. This configurable cache architecture is custom designed to operate correctly in Near-Threshold voltages, at sub 500 mV in 65 nm technology while tolerating a large number of Manufacturing Process Variation induced defects. Based on a smart relocation and resizing methodology, RDC-Cache decomposes the data that is targeted for a defective cache way and relocates one or more data words to a new location avoiding a write to defective bit locations. When servicing a read request, the requested data is reconstructed through an inverse operation. For the purpose of fault tolerance at low voltages the cache size is reduced, however, in this architecture the final cache size is considerably higher compared to previously suggested resizable cache organizations (Agarwal et al., Trans Solid State Circuits 40(9), 2005; Wilkerson et al., ISCA, 2008). The following three features (a) compaction of relocated words, (b) ability to use defective words for fault tolerance and (c) “linking” (relocating the defective word to any row in the next bank), allows this architecture to achieve far larger fault tolerance in comparison to Agarwal et al. (Trans Solid State Circuits 40(9)) and Wilkerson et al. (ISCA, 2008). In high voltage mode, the fault tolerant mechanism of RDC-Cache is turned-off with minimal (0.91 %) latency overhead compared to a traditional cache.

On-chip cache memories play an important role in resource-constrained embedded systems by filtering out most off-chip memory accesses. Because cache latency and energy consumption are generally proportional to cache sizes, a small cache at the top level of the memory hierarchy is desirable. Previous work has presented a novel cache architecture called a filter cache to reduce hit time and energy consumption of the L1 instruction cache. However, consideration to the data cache requires a different approach and has not been researched much. In this paper, we propose a filter data cache architecture to effectively adopt the filter cache to the data cache hierarchy. We observed that cache misses occur considerably and they are likely to be continuous when the filter cache is used for the data cache. Those misses cost performance and energy consumption by increasing cache latency and uploading unnecessary data. The proposed filter data cache architecture reduces miss costs using three schemes: early cache hit predictor (ECHP), locality-based allocation (LA), and No Tag Matching Write (NTW). Experimental results show that the proposed filter data cache reduces energy consumption of the data caches by 21% compared with the filter cache, and the energy consumption of the ALU by 27.2 percentage on average. The overheads in terms of area and leakage power are small and the proposed filter data cache architecture does not hurt performance.

A reconfigurable cache architecture for object-oriented application-specific instruction set processors (ASIP) is presented in this paper. The embedded ASIPs we follow in this research are specifically designed to suit object-oriented applications and are synthesized form an object-oriented high-level specification. The ASIPs are composed of a processor core along with a number of hardware functional units. In order to support concurrent execution of the functional units, we propose a cache architecture which is virtually divided into a number of partitions. The partition sizes can be dynamically changed depending on the run-time behavior of the application. Partitioning the cache not only provides the concurrent memory access for the functional units, but also reduces the number of tag comparisons per cache access. We also develop a simple and energy-efficient cache consistency mechanism among cache partitions. In this paper we evaluate the impact of the proposed cache architecture on the cache energy consumption, by implementing it in a number of our ASIPs. The results show that the proposed cache architecture reduces the number of tag comparisons per cache access by 39% on average

Energy consumption plays a crucial role in the design of embedded processors especially for portable devices. Since memory access consumes a significant portion of the energy of a processor, the design of fast low-energy caches has become a very important aspect of modern processor design. In this paper, we present a novel cache architecture for reduced energy instruction caches. Our proposed cache architecture consists of the L1 cache, multiple line buffers, and a prediction mechanism to predict which line buffer, or L1 cache to access next. We used simulation to evaluate our proposed architecture and compare it with the HotSpot cache, Filter cache, Predictive line buffer cache and Way-Halting cache. Simulation results show that our approach can reduce instruction cache energy consumption, on average, by 75% without sacrificing performance.

With climate change concerns on the rise, finding efficient and sustainable ways to separate carbon dioxide from industrial gas mixtures has become increasingly important. Membrane‐based gas separation technologies offer a promising solution due to their low energy consumption, low emissions, and ease of operation. In this study, we dug deep into theoretical energy consumption and practical optimization strategies for CO2 separation using such technologies. Our results showed that CO2 separation can be achieved with relatively low specific energy consumption, ranging from 0.09 to 0.27 MJe/kg CO2, depending on feed CO2 concentration. By conducting process simulations, we determined the optimal feed gas pressure and membrane surface area required to achieve a CO2 absorption ratio of 90% (mol). We also analyzed the effects of CO2 permeation and selectivity on energy consumption and membrane area, revealing that increasing both can significantly reduce energy consumption, albeit with more membrane surface area required. Using seepage flow circulation was found to be a particularly effective way to improve feed CO2 concentration and reduce energy consumption. To optimize and improve the capturing process, we conducted exergy analysis in each of the five stages of optimization, reporting Cooling Utilities (MW), Heating Utilities (MW), and Total Utilities (MW) for each step. Our results showed that in the optimal mode, Total Utilities (MW) were reported as 228.1, highlighting the potential of membrane‐based CO2 separation for carbon capture and storage applications. This study provides valuable insights and practical strategies for achieving efficient and sustainable CO2 separation.

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