A Generalized Reverse Conversion Algorithm for Six-Moduli Set

In the last years, investigation on residue number systems (RNS) has targeted parallelism and larger dynamic ranges. In this paper, we start from the moduli set {2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(</sup> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)/2+1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(</sup> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)/2+1} , with an equivalent 5 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -bit dynamic range, and propose horizontal and vertical extensions in order to improve the parallelism and increase the dynamic range. The vertical extensions increase the value of the power-of-2 modulus in the five-moduli set. With the horizontal extensions, new six channel sets are allowed by introducing the 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1+1 or 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -1+1 moduli. This paper proposes methods to design memoryless reverse converters for the proposed moduli sets with large dynamic ranges, up to (8 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)-bit. Due to the complexity of the reverse conversion, both the Chinese Remainder Theorem and the Mixed Radix Conversion are applied in the proposed methods to derive efficient reverse converters. Experimental results suggest that the proposed vertical extensions allow to reduce the area-delay-product up to 1.34 times in comparison with the related state-of-the-art. The horizontal extensions allow larger and more balanced moduli sets, resulting in an improvement of the RNS arithmetic computation, at the cost of lower reverse conversion performance.

In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional number system. The methods of reverse conversion for general form moduli based on the Chinese remainder theorem and the mixed-radix conversion are considered, as well as the optimized methods for special form moduli. A modified New CRT-I &amp; New CRT-II with conjugate moduli set is considered to implement adder, multipliers and subtractions with optimised algorithms. This paper mainly deals with the conversion of numbers from binary to RNS as well RNS to binary with the specific modulo {2^n±k} which proves this new method. Modified Radix16 booth encoding algorithm and square carry bypass adder are used in implementation of RNS system to reduce parameter constraints.

Residue number systems (RNS) offer unlimited opportunities for high performance arithmetic provided efficient forward and reverse converters can be constructed for the moduli set at hand. All forward conversion proposals to date require some read-only memory (ROM) along with computational elements like full adders (FA). Also, there is no single coherent approach for forward conversion design-each study proposes its own conversion philosophy. There is a clear need for a single parameterizable forward conversion model that can capture most of the important design parameters in the solution space. In this paper, we take the first step toward such a universal model. We show that by formulating the forward conversion problem in terms of modular exponentiation and addition, we can achieve memory free conversion. Furthermore, we generalize our solution such that bit serial and bit parallel implementations can be derived by simply varying a parameter. This allows the designer of the forward converter to ask what if questions and explore an optimal forward conversion solution. Apart from the formulation itself, the paper makes two other contributions. First, it demonstrates an entirely new set of converters that use no lookup. Second, we show how conversion complexity can be reduced significantly by sharing some of the circuitry over several forward converters.

The paper presents algorithms for the generation of Residue Number System (RNS) triples with $SQ=2^{k}-1$ and quadruples with $SQ=2^{k}$ for some k. Triples and quadruples allow us to design efficient hardware implementations of non-modular operations in RNS such as division, sign detection, comparison of numbers, reverse conversion with using of a diagonal function from requiring division with the remainder by the diagonal module SQ. Division with a remainder in the general case is the most complex arithmetic operation in computer technology. However, the consideration of special cases can significantly simplify this operation and increase the efficiency of hardware implementation. We show that there are 5573 good RNS triples (2301 even and 2372 odd) with elements less than 10 000, as the values of SQ vary from $2^{5}-1$ to $2^{27}-1$ . In contrast, RNS quadruples with $SQ=2^{k}$ seem to be quite rare. Restricting our search to sums of the elements in a quadruple less than 4000 we find that exactly 31 such quadruples exist. Their values of SQ vary between 220 and 230 with always even exponent. We suggest the measure of RNS balance and find perfectly balanced RNS among triples according to this measure. We demonstrate the advantages of more balanced quadruples by means of hardware implementation.

The architecture of a fault-tolerant modular neurocomputer based on modular number projections

Sign detector is an important unit of the residue number system (RNS) for numerous digital signal processing applications. It has received considerably less attention than its reverse conversion and scaling problems. However, the sign detection is essentially required for residue number comparison, division and other difficult arithmetical operations in RNS. In this contribution, a sign detection algorithm for classical moduli-set $\{2^{n}-1,2^{n}, 2^{n}+1\}$ is proposed with less complex architecture by using scaling technique. The proposed sign detector circuit is implemented using a carry save adder (CSA), a carry-generation circuit and a simplified parallel prefix adder. The proposed algorithm is synthesized using design compiler of Synopsys tool and compared against the available literatures for the same moduli-set. The proposed design exhibits considerable reduction in time-delay, area and power as compared to others.

The authors discuss employing alternative number systems to reduce power dissipation in portable devices and high-performance systems. They focus on two alternative number systems that are quite different from the conventional linear number representations, namely the logarithmic number system (LNS) and the residue number system (RNS). Both have recently attracted the interest of researchers for their low-power properties. The authors address aspects of the conventional arithmetic representations, the impact of logarithmic arithmetic on power dissipation, and discuss the low-power aspects of residue arithmetic.

Recent trends like increasing operating frequencies, larger die sizes and demand for greater portability make power reduction a hard taskmaster. It is acknowledged that the greatest returns come from optimization at the architectural and technology level. We present, for the first time, residue architectures that reduce the power by more than 70% without changes in technology. This reduction is achieved without sacrificing performance and with minimal sacrifice in area (less than 60%). The key to such low power solutions is trading-off the speed gained by parallelism for lower power. Existing proposals that achieve similar trade-offs demand an area increase of more than a factor of two and also increased control complexity. Other benefits of using residue arithmetic for low power is the significant reduction in peak current and increased design locality. The role of the number of computations per forward (or reverse) conversion in determining the power characteristics of the system are also analyzed and explained. The effectiveness of the methodology is illustrated using a system that extracts a 256-point FFT of the input signal.

The residue number system (RNS) allows high accuracy integer-valued arithmetic operations to be decomposed into independent (carry-free), low accuracy computations that can be performed in parallel. The RNS thus provides an attractive alternative to weighted number systems (e.g., binary or decimal) for high speed numerical computing1. The residue number representation is completely specified by a set of relatively prime moduli. The overall dynamic range is given by the product fo the moduli. Although this dynamic range can be arbitrarily high, the dynamic range required in any individual subcalculation is commensurate only with the associated modulus. The RNS also leads to a reduction in the growth of the total number of combinatorial logic elements required to perform a calculation via truth table approach. Specifically, the RNS exhibits additive growth in spatial complexity with input word size, contrasted by multiplicative (exponential) growth for weighted number systems.

In this brief, we evaluate two techniques for obtaining mixed-radix digits using mixed-radix conversion technique, for the residue number system (RNS) moduli set {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> , 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n+1</sup> -1}. These are needed for comparison of two numbers in residue form, base extension to modulus 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n+e</sup> and reverse conversion. The complete architectures are derived to estimate the hardware resource requirement and computation time for deriving the mixed-radix digits. The proposed techniques are also compared with designs based on other techniques available in literature. The trade-offs regarding hardware resource requirement, computation time and power dissipation are brought out.

A new Mixed Radix Conversion algorithm MRC-II

In this paper, two residue number system (RNS) to binary converters for the moduli set { $$2^{n}, 2^{n-1}-1,2^{n}-1, 2^{n+1}-1\}$$ for (n even) are presented. One of them uses a two-level conversion, in which, in the first level, two pairs of moduli are considered to obtain two intermediate decoded numbers. A second-level converter obtains the final decoded number corresponding to these two intermediate decoded numbers. Both levels use mixed radix conversion. The second proposed RNS to binary converter uses the conventional MRC of the four-moduli set. The proposed converters are compared with previously reported conversion techniques for this moduli set and converters for other four, five and eight moduli sets for realizing similar dynamic ranges regarding hardware requirement and conversion time. The hardware resource requirement (A), conversion time (T), AT and $$AT^{2}$$ trade-offs are discussed to bring out the relative advantages of various converters. The proposed converters have been shown to need less hardware or less conversion time than the other some of the reported converters for this moduli set. It has been shown by detailed comparison that converters using conjugate moduli and vertical extension generally exhibit better performance (lower hardware /lower conversion time) than those using no vertical extension, while needing differing word lengths of various moduli. These, however, need slightly complex multipliers/adders in the $$(2^{n} +1)$$ channel. Implementation results on FPGA of the proposed converters for few dynamic ranges also have been presented.

The Residue Number System (RNS) is a non-positional number system that represent number in the form of residues modulo a set of coprime moduli. This nature of RNS makes it advantageous in achieving carry-free arithmetic. However, due to the non-positional nature of RNS, direct number comparisons to determine the magnitude of RNS numbers is nearly impossible. In this paper, a magnitude comparison scheme is proposed and is theoretically proven and evaluated. The proposed scheme compares the relative magnitude of any two RNS numbers via sign detection. It first computes the modular differences of the residues of the two RNS numbers, and , and then computes the sum of the results, ,which is then proven to be equal to zero. The final implementation of the technique requires the reverse conversion of . Then sign detection is performed on and the results determine whether or . Further analysis proves that the proposed scheme accurately compares the magnitude of any two RNS numbers, whether a signed or unsigned number. The proposed scheme was evaluated and compared with another state-of-the-art scheme based on three key matrices, Area, Delay and Area-Delay product. The proposed scheme outperformed the state-of-the-art scheme in all three-matrix evaluations.

New efficient residue-to-weighted converters for multi-moduli residue number systems (RNS) based on sets {2/sup n1/-1, 2/sup n1/+1, 2/sup n2/-1, 2/sup n2/+1, ..., 2/sup nL/-1, 2/sup nL/+1} are presented. The moduli 2/sup n/-1 and 2/sup n/+1 are called conjugates of each other. The benefits offered by multi-moduli RNS processors relying on sets with pairs of conjugate moduli are: (1) large dynamic ranges, (2) fast and balanced RNS arithmetic, (3) simple and efficient RNS processing hardware, and (4) efficient weighted-to-RNS and RNS-to-weighted converters. The new converters presented in this paper are hardware-efficient since all the modulo adders required by them are adders mod(2/sup n/-1) which can easily be implemented as 1's complement adders. Furthermore, the largest such modulo adder is an adder modulo the square root of the system's dynamic range instead of modulo the entire dynamic range.

Modular arithmetic units for friendly moduli are crucial for residue number system (RNS) applications. Choosing a moduli set of the form is expected to provide maximum benefits for modular arithmetic performance. In this respect, this paper proposes a hardware architecture for the moduli set (with even), in particular an efficient architecture for the reverse conversion, which is often the bottleneck of RNS processors. The main idea is to remove the CRT multiplicative inverse from the reverse conversion stage, achieving scalable hardware with reduced complexity. We show that the modular multiplication of the multiplicative inverse can be transferred to the arithmetic channels with minimal overhead while reaching outstanding gains in the scalable reverse conversion stage. Furthermore, the presented method enables the utilization of recent hardware reutilization strategies to attain further improvements. Results show that the proposed reverse converter outperforms the state of the art by 17.48% in delay and 53.47% in area for . Advantages become even more substantial for larger values of .