Optical Outer Product Look-up Table Architectures for Residue Arithmetic

In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional number system. The methods of reverse conversion for general form moduli based on the Chinese remainder theorem and the mixed-radix conversion are considered, as well as the optimized methods for special form moduli. A modified New CRT-I & New CRT-II with conjugate moduli set is considered to implement adder, multipliers and subtractions with optimised algorithms. This paper mainly deals with the conversion of numbers from binary to RNS as well RNS to binary with the specific modulo {2^n±k} which proves this new method. Modified Radix16 booth encoding algorithm and square carry bypass adder are used in implementation of RNS system to reduce parameter constraints.

Wideband chaotic carrier is a promising solution for wideband communication, since it overcomes the disadvantages of both narrowband and spread-spectrum communication. It is particularly suited to realize information encryption for secure communication. Chaotic signals can be generated by using discrete-time non-linear dynamical circuits, since they can exhibit a quasi-chaotic (QC) behavior. A particular implementation of QC digital filters can be based on finite precision arithmetic and, in particular, on residue number system (RNS) circuits, which possess very attractive features with regard to their VLSI implementation. In the present paper, we propose an RNS architecture that can be used in connection with secure communication. Each RNS channel consists of a QC oscillator, having its coefficients belonging to a Galois field defined by a prime modulus. In particular, the QC behavior is ensured by well-known properties of primitive polynomials in this field, which generate the characteristic feedback of the oscillator. We demonstrate in the paper that the proposed RNS architecture yields a cost-effective VLSI implementation, which favorably compares with respect to other secure communication approaches proposed in the technical literature. We obtain encouraging results both in terms of confidentiality of the encrypted information and of throughput rate for real-time applications. Moreover, we propose an extended architecture suited to the protection of the secure communication system against transmission errors, by using the self-correcting ability of Redundant RNS (RRNS).

New efficient residue-to-weighted converters for multi-moduli residue number systems (RNS) based on sets {2/sup n1/-1, 2/sup n1/+1, 2/sup n2/-1, 2/sup n2/+1, ..., 2/sup nL/-1, 2/sup nL/+1} are presented. The moduli 2/sup n/-1 and 2/sup n/+1 are called conjugates of each other. The benefits offered by multi-moduli RNS processors relying on sets with pairs of conjugate moduli are: (1) large dynamic ranges, (2) fast and balanced RNS arithmetic, (3) simple and efficient RNS processing hardware, and (4) efficient weighted-to-RNS and RNS-to-weighted converters. The new converters presented in this paper are hardware-efficient since all the modulo adders required by them are adders mod(2/sup n/-1) which can easily be implemented as 1's complement adders. Furthermore, the largest such modulo adder is an adder modulo the square root of the system's dynamic range instead of modulo the entire dynamic range.

In the recent days, the exponential growth in functionality of mobile devices leads the manufacturers to develop more and more sophisticated microprocessors and microcontrollers. The power requirements of the microprocessors are increasing day by day along with the processing speed and chip area. So, rather than traditional number systems, Residue Number System (RNS) is becoming attractive for their capabilities for performing addition and multiplication operation efficiently. In this paper, based on the formulation of the Chinese remainder theorem and RNS, a guideline for a Reconfigurable DSP Processor is proposed that can process some predefined functions. As RNS minimizes the carry propagation, the scheme can be implemented in Mobile and Wireless Computing and other fields where high speed computations are required with limited resources.

Residue Number System has emerged as an alternative number system with advantages in many real-life systems including in digit signal processing devices. Computational systems built on residue number system require both forward and reverse conversion processes. These converters respectively convert a given integer into its corresponding residues and calculate the original integer from its residues. While forward conversion is pretty straight forward, reverse conversion poses challenges often requiring difficult procedures. Much of residue number system research has therefore been devoted to design and implementation of efficient reverse conversion algorithm. The Chinese Reminder Theorem and the Mixed-Radix Conversion are the two popular ones. The Chinese Reminder Theorem results in complex circuitry that requires difficult computation involving large modulo-M values. The Mixed-Radix Conversion offers simplicity in designs although its steps are sequential. This paper proposes a generalized reverse conversion algorithm tailored for a six-moduli set with a large dynamic range. This innovative algorithm minimises the difficult multiplicative inverse operations found in the traditional reverse conversion methods paving the way for a more efficient reverse conversion processes for systems that requires high dynamic ranges. The new algorithm has been meticulously evaluated numerically on a proposed six-moduli set $\left\{2^{n+1}-1,2^{2 n}+1,2^{2 n+1}-1,2^{3 n}+1,2^{3 n+1}-1,2^{4 n}+1\right\}$ for even values of , to ensure its correctness and simplicity. The approach holds great promise for enhancing the development of reverse converters allowing the expansion of the landscape of residue number system.

Elliptic Curve Cryptography operations rely heavily on the strong security of scalar multiplication. However, this operation is vulnerable to side channel (SCA) and fault injection (FA) attacks. The use of alternative arithmetic systems like Residue Number System (RNS) for all scalar multiplication underline operations has been proposed as an efficient countermeasure approach for the above attacks. In RNS, a number is represented as a set of smaller numbers, where each one is the result of the modular reduction with a given moduli basis. Under certain requirements, a number can be uniquely transformed from the integers to the RNS domain (and vice versa) and all arithmetic operations can be performed in RNS. This representation provides an inherent SCA and FA resistance to many attacks and can be further enhanced by additional RNS arithmetic manipulations or more traditional algorithmic countermeasures. In this paper, extending our previous work, we explore the potentials of RNS as an SCA and FA countermeasure. A description of RNS based SCA and FA resistance means is provided through appropriate scalar multiplication algorithmic variations, traces of the proposed algorithm are collected and the results are analyzed regarding the RNS countermeasure strength. More specifically, in this paper, a secure RNS based Montgomery Power Ladder based scalar multiplication algorithm is provided and is implemented on an ARM Cortex A7 processor. The implementation SCA-FA resistance is evaluated by collecting preliminary leakage trace results that validate our initial assumptions.

In the last years, investigation on residue number systems (RNS) has targeted parallelism and larger dynamic ranges. In this paper, we start from the moduli set {2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(</sup> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)/2+1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(</sup> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)/2+1} , with an equivalent 5 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -bit dynamic range, and propose horizontal and vertical extensions in order to improve the parallelism and increase the dynamic range. The vertical extensions increase the value of the power-of-2 modulus in the five-moduli set. With the horizontal extensions, new six channel sets are allowed by introducing the 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1+1 or 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -1+1 moduli. This paper proposes methods to design memoryless reverse converters for the proposed moduli sets with large dynamic ranges, up to (8 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)-bit. Due to the complexity of the reverse conversion, both the Chinese Remainder Theorem and the Mixed Radix Conversion are applied in the proposed methods to derive efficient reverse converters. Experimental results suggest that the proposed vertical extensions allow to reduce the area-delay-product up to 1.34 times in comparison with the related state-of-the-art. The horizontal extensions allow larger and more balanced moduli sets, resulting in an improvement of the RNS arithmetic computation, at the cost of lower reverse conversion performance.

Fully Homomorphic Encryption (FHE) permits processing information in the form of ciphertexts without decryption. It can ensure the security of information in common technologies used today, such as cloud computing, the Internet of Things, and machine learning, among others. A primary disadvantage for its practical application is the low efficiency of sign and comparison operations. Several FHE schemes use the Residue Number System (RNS) to decrease the time complexity of these operations. Converting from the RNS to the positional number system and calculating the positional characteristic of a number are standard approaches for both operations in the RNS domain. In this paper, we propose a new method for comparing numbers and determining the sign of a number in RNS. We focus on the even ranges that are computationally simple due to their peculiarities. We compare the performance of several state-of-art algorithms based on an implementation in C++ and relatively simple moduli with a bit depth from 24 to 64 bits. The experimental analysis shows a better performance of our approach for all the test cases; it improves the sign detection between 1.93 and 15.3 times and the number comparison within 1.55–11.35 times with respect to all the methods and configurations.

Algorithms are developed to compute the number of active devices for residue number system (RNS) and binary number system (BNS) signal processing architectures. The precharged CMOS technology is used in order to build the filter architecture. The ROM lookup table and two's complement multiplier are used as the computational cells in the RNS and BNS, respectively. A direct implementation transversal systolic filter architecture is considered in RNS and BNS algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The scaling operation, i.e. the division by a constant factor followed by rounding, is a commonly used technique for reducing the dynamic range in digital signal processing (DSP) systems. Usually, the constant is a power of two, and the implementation of the scaling is reduced to a right shift. This basic operation is not easily implementable in the residue number system (RNS) due to its non positional nature. A number of different algorithms have been presented in the literature for the RNS scaling. In this paper, several RNS dynamic reduction techniques have been analyzed and the selected one is applied to a polyphase filter bank. A comparison of the filter bank scaled with RNS to binary and binary to RNS conversions, and the RNS scaled implementation is presented. A reduction of area and power consumption of about 30% for the scaling block is obtained.

Creation of reliable and secure cloud storage is a complicated task, since this type of data storage and processing is efficient and cost effective. The Residue Number System (RNS) can be used to achieve the required level of data security and reliability. RNS is a non-positional number system, the use of which for data protection is promising. Redundant RNS allows the creation of correction codes. Such properties of error-correction codes as effectiveness, safety and reliability depend on the redundancy of the RNS. This paper evaluates the effectiveness of the RNS correction codes usage in multi-cloud data storage and processing systems by examining various sets of RNS moduli.

The architecture of a fault-tolerant modular neurocomputer based on modular number projections

The Residue Number System (RNS) is a non-positional number system that represent number in the form of residues modulo a set of coprime moduli. This nature of RNS makes it advantageous in achieving carry-free arithmetic. However, due to the non-positional nature of RNS, direct number comparisons to determine the magnitude of RNS numbers is nearly impossible. In this paper, a magnitude comparison scheme is proposed and is theoretically proven and evaluated. The proposed scheme compares the relative magnitude of any two RNS numbers via sign detection. It first computes the modular differences of the residues of the two RNS numbers, and , and then computes the sum of the results, ,which is then proven to be equal to zero. The final implementation of the technique requires the reverse conversion of . Then sign detection is performed on and the results determine whether or . Further analysis proves that the proposed scheme accurately compares the magnitude of any two RNS numbers, whether a signed or unsigned number. The proposed scheme was evaluated and compared with another state-of-the-art scheme based on three key matrices, Area, Delay and Area-Delay product. The proposed scheme outperformed the state-of-the-art scheme in all three-matrix evaluations.

Abstract—A new residue number system algebra has been previously proposed by the author. The algebra has solved an essential theoretical barrier in the residue number system and has enabled one to pursue additive operations in the residue number system to their full extent, overcoming such difficulties as restrictions on the sign or magnitude of numbers in the system. In this paper, basic theorems in the algebra are introduced first, and then, based on the theorems, table look-up oriented solutions for hardware overflow checking, sign detection, and floating-point additive operations are given. The theorems expound the behavior of a quantity treated as a veiled mysterious function in the literature. To the best knowledge of the author, hardware overflow-checking schemes and floatingpoint additive operations in the residue number system have never been reported elsewhere. So far, the upper limit of the magnitude of numbers in the system ever discussed has been the one that is theory-limited, and floating-point operations in the residue number system have never been discussed.

The paper presents algorithms for the generation of Residue Number System (RNS) triples with $SQ=2^{k}-1$ and quadruples with $SQ=2^{k}$ for some k. Triples and quadruples allow us to design efficient hardware implementations of non-modular operations in RNS such as division, sign detection, comparison of numbers, reverse conversion with using of a diagonal function from requiring division with the remainder by the diagonal module SQ. Division with a remainder in the general case is the most complex arithmetic operation in computer technology. However, the consideration of special cases can significantly simplify this operation and increase the efficiency of hardware implementation. We show that there are 5573 good RNS triples (2301 even and 2372 odd) with elements less than 10 000, as the values of SQ vary from $2^{5}-1$ to $2^{27}-1$ . In contrast, RNS quadruples with $SQ=2^{k}$ seem to be quite rare. Restricting our search to sums of the elements in a quadruple less than 4000 we find that exactly 31 such quadruples exist. Their values of SQ vary between 220 and 230 with always even exponent. We suggest the measure of RNS balance and find perfectly balanced RNS among triples according to this measure. We demonstrate the advantages of more balanced quadruples by means of hardware implementation.