A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

The various codes are used for the error detection and correction in the field of communication. Some are for the single bit error and some are for the multiple bits error. Reed-Muller algorithm realizes the ability of multiple bits error detection and correction. With the superior error correction capability, these codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. Reed-Muller codes cover a wide range of service requirements and diverse interference conditions in wireless applications and can operate at both high and low code rates. In this paper, the comparison of Reed-Muller codes with different other codes for error detection and correction of multiple bits is proposed and further we can implement it on a Xilinx field programmable gate array (FPGA) device. Using Reed-Muller method the data is transferred from transmitter to receiver without any error. The error detection and correction principle and realization methods are described in detail. The multiple bits error detection and correction with Reed-Muller algorithm method can improve the bit error rate and packet error rate effectively.

This work shares the observations of stuck bits by proton beam in DDR3 components in 3x-nm technologies. The DDR3 SDRAMs from four major DRAM manufacturers were tested with a 45-MeV proton beam at an operating frequency of 800 MHz. The beam exposure resulted in single bit upset (SBU) and multiple bit upsets (MBUs), as well as single and multiple stuck bits in a word due to micro-dose and displacement damage effects. The number of stuck bits reduced as the refresh interval duration was decreased. Moreover, for the tested samples, the stuck bits were recovered completely and could be run in the normal operation mode after annealing at 150 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C. The occurrence of multiple stuck bits in a word was likely due to damages to the control logic and those stuck bits were recovered as well after annealing at 150 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C.

It has been shown previously that adaptive filters can be designed with hardware redundancy so they can continue operating effectively after the occurrence of certain types of hardware failures, thereby achieving reliability through a mechanism known as adaptive fault tolerance. This paper examines the capabilities of adaptive fault tolerance in cases of single and multiple bit errors in the adaptive filter coefficients using floating-point number representation.

Due to scaling in CMOS technology, multiple bit upsets (MBUs) have been widely occurred in memories. As a result, multiple adjacent bits of memories are corrupted and valuable information are lost forever. To mitigate these problems, multi-bit adjacent error-correcting codes are generally employed in SRAM memories. Single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are used to mitigate radiation or noise source induced MBUs to protect static random access memory (SRAM) devices. These codes are able to correct single and double adjacent errors, and also detect double errors. In this paper, three different SEC-DED-DAEC codes have been designed and implemented for SRAM memories. All functional blocks of these codecs are simulated and synthesized both in FPGA and ASIC platforms. Performances of the different SEC-DED-DAEC codes are observed in terms of area and delay.

Spin Transfer Torque Magnatic Random Access Memory (STT-MRAM) has the potential to become a universal memory technology due to its various attractive features such as non-volatility, high density, CMOS compatibility and zero leakage. However, STT-MRAM suffers from high write latency and poor reliability compared to SRAM. This is primarily due to its stochastic nature of switching, which makes it not suitable for fast caches such as L1. The use of robust Error Correction Coding (ECC) with multiple bit correction capability to optimize the write margin and reliability results in large decoding latencies and large number of check bits. In this paper, we propose a new solution to exclude the high costs of using ECC in terms of decoding latency and storage overhead to be able to use STT-MRAM for fast caches. We exploit the fact that STT-MRAM poses asymmetric errors due to the nature of Magnetic Tunnel Junction (MTJ) cell, which makes ECC a pessimistic solution to address such errors. Therefore, efficient Systematic Unidirectional Error-Detecting Code (SEDC) is proposed to be adopted instead of conventional ECC combined with proper cache access mechanism to fetch correct data in case of error detection. Our proposed approach provides orders of magnitude better reliability and considerable performance improvement that makes STT-MRAM viable for fast-caches compared to the existing solutions.

Correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single chip output and simultaneously detecting errors caused by single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting-Single b-bit byte Error Detecting (S/sub t/b/EC-S/sub b/ED) codes which have the capability of correcting random t-bit errors occurring within a single b-bit byte and simultaneously indicating single b-bit byte errors. For the practical case where the chip data output is 8 bits, i.e., b = 8, the S/sub 3/8/EC-S/sub 8/ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S/sub 3/8/EC-S/sub 8/ED code is capable of correcting errors caused by single subarray data faults, i.e., single 4-bit byte errors, as well. This paper also shows that perfect S/sub (b-t)/b/EC-S/sub b/ED codes, i.e., perfect S/sub t/b/EC-S/sub b/ED codes for the case where t = b - 1, do exist and provides a theorem to construct these codes.

In many medical applications, feature selection is obvious; but in medical domains, selecting features and creating a feature vector may require more effort. The wavelet transform (WT) technique is used to identify the characteristic points of an electrocardiogram (ECG) signal with fairly good accuracy, even in the presence of severe high-frequency and low-frequency noise. Principal component analysis (PCA) is a suitable technique for ECG data analysis, feature extraction, and image processing — an important technique that is not based upon a probability model. The aim of the paper is to derive better diagnostic parameters for reducing the size of ECG data while preserving morphology, which can be done by PCA. In this analysis, PCA is used for decorrelation of ECG signals, noise, and artifacts from various raw ECG data sets. The aim of this paper is twofold: first, to describe an elegant algorithm that uses WT alone to identify the characteristic points of an ECG signal; and second, to use a composite WT-based PCA method for redundant data reduction and better feature extraction. PCA scatter plots can be observed as a good basis for feature selection to account for cardiac abnormalities. The study is analyzed with higher-order statistics, in contrast to the conventional methods that use only geometric characteristics of feature waves and lower-order statistics. A new algorithm — viz. PCA variance estimator — is developed for this analysis, and the results are also obtained for different combinations of leads to find correlations for feature classification and useful diagnostic information. PCA scatter plots of various chest and augmented ECG leads are obtained to examine the varying orientations of the ECG data in different quadrants, indicating the cardiac events and abnormalities. The efficacy of the PCA algorithm is tested on different leads of 12-channel ECG data; file no. 01 of the Common Standards for Electrocardiography (CSE) database is used for this study. Better feature extraction is obtained for some specific combinations of leads, and significant improvement in signal quality is achieved by identifying the noise and artifact components. The quadrant analysis discussed in this paper highlights the filtering requirements for further ECG processing after performing PCA, as a primary step for decorrelation and dimensionality reduction. The values of the parameters obtained from the results of PCA are also compared with those of wavelet methods.

Modern nanoscale devices with storage capacity typically implement error correction codes (ECCs) in order to cope with the effects of natural radiation. Thus, different state-of-the-art ECC techniques aim at preventing data corruption when different numbers of errors (or bitflips) occur in the same logical memory word. However, even though bit interleaving prevents a single particle (such as a proton or a neutron) from flipping several cells in the same word, it cannot be discarded that two independent events may affect nearby cells in the same word and, therefore, would provoke a multiple bit upset (MBU) or equivalent. This article studies the reliability of various state-of-the-art ECC techniques designed for memories to maintain their data integrity under radiation or any other hazardous conditions, where said event accumulation is likely to occur. For this purpose, a set of easy-to-use equations will be provided to estimate the probability of error occurrence in a memory that implements different ECCs, as a function of the number of accumulated bitflips, size of the memory, and word size.

In Ultra Deep Sub Micron (UDSM) Technology, accomplishment of error free data transmission through Network on Chip (NoC) interconnect becomes impractical. This difficult state is widely managed by the use of Error Correction Codes (ECC) in NoC. A novel Hamming based Multiple Transient Error Correction (HMTEC) code is proposed to enhance the NoC interconnect reliability. Implementation of this code corrects all single bit errors and most of the combinations of errors upto 8 bits for a flit size of 32. Furthermore, this code allows error correction in both data and redundant bits. This coding method is performed at lower power consumption, area occupancy and delay when measured against similar codes proposed in recent years.

The question to what extent particle induced transients in combinational parts of a circuit propagate into memory elements is addressed in this paper An experimental method is presented in which the proportion of bit flips originating from heavy-ion hits in combinational logic is determined. It is proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. The proportion of all transients in combinational logic that were latched into registers was experimentally, estimated to be between 0.7/spl middot/10/sup -3/ and 2/spl middot/10/sup -3/ for a custom designed CMOS circuit. Very few multiple bit flips were observed during the experiments which indicates that the single bit flip model used in many high-level simulations is reasonable accurate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The present work demonstrates the utilization of computer-aided diagnosis system for the detection of lung cancer diseases using computer tomography (CT) images, magnetic resonance images (MRI) and X-ray images. The feature extraction process in lung cancer images has been achieved by scale invariant feature transform (SIFT), speeded up robust features (SURF), and principal component analysis (PCA) techniques. In this work, a comparative investigation of different feature extraction technique such as SIFT, SURF, and PCA has been discussed in order to find the best descriptor for feature extraction of cancerous subjects to the normal subjects in terms of two parameters named as execution time and error rate. The main aspect of these learning approaches is to find the valid key points in minimum execution time with least error. The results reveal that the SURF technique has an average execution time of 0.448 s with an average error rate value of 25.704 which is least among three techniques. Hence, SURF extraction technique is best as compared to SIFT and PCA.

Bose–Chaudhuri–Hocquenghem (BCH) codes are broadly used to correct errors in flash memory systems and digital communications. These codes are cyclic block codes and have their arithmetic fixed over the splitting field of their generator polynomial. There are many solutions proposed using CPUs, hardware, and Graphical Processing Units (GPUs) for the BCH decoders. The performance of these BCH decoders is of ultimate importance for systems involving flash memory. However, it is essential to have a flexible solution to correct multiple bit errors over the different finite fields (GF(2)). In this paper, we propose a pragmatic approach to decode BCH codes over the different finite fields using hardware circuits and GPUs in tandem. We propose to employ hardware design for a modified syndrome generator and GPUs for a key-equation solver and an error corrector. Using the above partition, we have shown the ability to support multiple bit errors across different BCH block codes without compromising on the performance. Furthermore, the proposed method to generate modified syndrome has zero latency for scenarios where there are no errors. When there is an error detected, the GPUs are deployed to correct the errors using the iBM and Chien search algorithm. The results have shown that using the modified syndrome approach, we can support different multiple finite fields with high throughput.

Manufacturers are continuously pushing NAND flash memory into smaller geometries and enforce each cell to store multiple bits in order to largely reduce its cost. Unfortunately, these scaling down techniques inherently degrade the endurance and reliability of flash memory. As a result, permanent errors such as block or die failures could occur with a higher possibility. While most transient errors like programming errors can be fixed by an ECC (error correction code) scheme, rectifying permanent errors requires a data redundancy mechanism like RAID (redundant array of independent disks) in a single SSD where multiple channels work in parallel. To enhance the reliability of a solid-state drive (SSD) while maintaining its performance, we first implement several common RAID structures in the channel level of a single SSD to understand their impact on an SSD's performance. Next, we propose a new data redundancy architecture called CR5M (Channel-RAID5 with Mirroring), which can be applied to one SSD for mission-critical applications. CR5M utilizes hidden mirror chips to accelerate the performance of small writes. Finally, we conduct extensive simulations using real-world traces and synthetic benchmarks on a validated simulator to evaluate CR5M. Experimental results demonstrate that compared with CR5 (Channel-RAID5) CR5M decreases mean response time by up to 25.8%. Besides, it reduces the average writes per channel by up to 23.6%.

By using the pulsed laser single effect facility, the single event upset and latch-up phenomenon are studied, and the bitmap of 90 nm complementary metal oxide semiconductor (CMOS) static random-access memory (SRAM) is mapped. It is shown that many multiple bit upsets occur and pulsed supply current of 20 mA amplitude is monitored. Based on the technology computer aided design (TCAD), it is found that the localized latch-up in CMOS SRAM is the main reason for the single event multiple bit upsets. Finally, by analyzing the results of the pulsed laser experiment and TCAD, it is found that the P/N well potential collapse is the key physical mechanism responsible for the spreading of the single event latch-up effect in 90 nm CMOS SRAM.

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes