A heuristic method for obstacle avoiding group Steiner tree construction

We consider the problem of finding a shortest rectilinear Steiner tree for a given set of points in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if we intersect the Steiner tree with some obstacle, then no connected component of the induced subtree must be longer than a given fixed length L. This kind of length restriction is motivated by its application in VLSI design where a large Steiner tree requires the insertion of buffers (or inverters) which must not be placed on top of obstacles. We show that the length-restricted Steiner tree problem can be approximated with a performance guarantee of 2 in O(n logn) time, where n denotes the size of the associated Hanan grid. Optimal length-restricted Steiner trees can be characterized to have a special structure. In particular, we prove that a certain graph, which is a variant of the Hanan grid, always contains an optimal solution. Based on this structural result, we can improve the performance guarantee of approximation algorithms for the special case that all obstacles are of rectangular shape or of constant complexity, i.e. they are represented by at most a constant number of edges. For such a scenario, we give a $\frac{5}{4}\alpha$ -approximation and a $\frac{2k}{2k-1}\alpha$ -approximation for any integral k ≥ 4, where α denotes the performance guarantee for the ordinary Steiner tree problem in graphs.

The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NP-hard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST heuristics is the Batched Iterated 1-Steiner (BI1S) heuristic of Kahng and Robins (1992). In a recent development, exact RST algorithms have witnessed spectacular progress: the new release of the GeoSteiner code of Warme, Winter, and Zachariasen (1998) has average running time comparable to that of the fastest available Bl1S implementation, due to Robins. We are thus faced with the paradoxical situation that an exact algorithm for an NP-hard problem is competitive in speed with a state-of-the-art heuristic for the problem. The main contribution of this paper is a new RST heuristic, which has at its core a recent 3/2 approximation algorithm of Rajagopalan and Vazirani (1999) for the metric Steiner tree problem on quasi-bipartite graphs-these are graphs that do not contain edges connecting pairs of Steiner vertices. The RV algorithm is built around the linear programming relaxation of a sophisticated integer program formulation, called the bidirected cut relaxation. Our heuristic achieves a good running time by combining an efficient implementation of the RV algorithm with simple, but powerful geometric reductions. Experiments conducted on both random and real VLSI instances show that the new RST heuristic runs significantly faster than Robins' implementation of BI1S and than the GeoSteiner code. Moreover, the new heuristic typically gives higher-quality solutions than Bl1S.

Routing is a crucial stage in the physical design of Very Large Scale Integration (VLSI) circuits, comprising three phases: global routing, track assignment routing, and detailed routing. With the development of VLSI circuits, scholars have proposed various track assignment routing algorithms. However, improving the efficiency of track assignment routing and optimizing conflicting design rules have become bottlenecks in track assignment routing problems. This study addresses these bottlenecks by utilizing single-level horizontal and vertical Steiner trees to extract routability information of local wire nets, resolving the adaptation issue between global routing and detailed routing. The proposed algorithm enhances routability information by an average of 16.07% across ten benchmark circuits. Additionally, a Generative Neural Network model based on Conditional Variational Autoencoder (CVAE) is employed to improve the efficiency of track assignment routing, yielding significant simulation results. Furthermore, a negotiation-based tear-and-reassign approach is utilized to address track congestion issues, resulting in an average optimization of 26.03% in overlap cost, with a tradeoff of sacrificing 6.67% of wirelength on average.

The Steiner tree problem is one of the fundamental optimization problems in distributed graph algorithms. Recently Saikia and Karmakar [27] proposed a deterministic distributed algorithm for the Steiner tree problem that constructs a Steiner tree in \(O(S + \sqrt{n} \log ^* n)\) rounds whose cost is optimal upto a factor of \(2(1 - 1/\ell )\), where n and S are the number of nodes and shortest path diameter [17] respectively of the given input graph and \(\ell \) is the number of terminal leaf nodes in the optimal Steiner tree. The message complexity of the algorithm is \(O(\varDelta (n - t) S + n^{3/2})\), which is equivalent to \(O(mS + n^{3/2})\), where \(\varDelta \) is the maximum degree of a vertex in the graph, t is the number of terminal nodes (we assume that \(t < n\)), and m is the number of edges in the given input graph. This algorithm has a better round complexity than the previous best algorithm for Steiner tree construction due to Lenzen and Patt-Shamir [21]. In this paper we present a deterministic distributed algorithm which constructs a Steiner tree in \(\tilde{O}(S + \sqrt{n})\) rounds and \(\tilde{O}(mS)\) messages and still achieves an approximation factor of \(2(1 - 1/\ell )\). Note here that \(\tilde{O}(\cdot )\) notation hides polylogarithmic factors in n. This algorithm improves the message complexity of Saikia and Karmakar’s algorithm by dropping the additive term of \(O(n^{3/2})\) at the expense of a logarithmic multiplicative factor in the round complexity. Furthermore, we show that for sufficiently small values of the shortest path diameter \((S=O(\log n))\), a \(2(1 - 1/\ell )\)-approximate Steiner tree can be computed in \(\tilde{O}(\sqrt{n})\) rounds and \(\tilde{O}(m)\) messages and these complexities almost coincide with the results of some of the singularly-optimal minimum spanning tree (MST) algorithms proposed in [9, 12, 23].

A rectilinear Steiner tree for a set T of points in the plane is a tree which connects T using horizontal and vertical lines. In the Rectilinear Steiner Tree problem, input is a set T of n points in the Euclidean plane (R^2) and the goal is to find an rectilinear Steiner tree for T of smallest possible total length. A rectilinear Steiner arborecence for a set T of points and root r in T is a rectilinear Steiner tree S for T such that the path in S from r to any point t in T is a shortest path. In the Rectilinear Steiner Arborescense problem the input is a set T of n points in R^2, and a root r in T, the task is to find an rectilinear Steiner arborescence for T, rooted at r of smallest possible total length. In this paper, we give the first subexponential time algorithms for both problems. Our algorithms are deterministic and run in 2^{O(sqrt{n}log n)} time.

Obstacle-avoiding Steiner minimal tree (OASMT) construction has become a focus problem in the physical design of modern very large-scale integration (VLSI) chips. In this article, an effective algorithm is presented to construct an OASMT based on X-architecturex for a given set of pins and obstacles. First, a kind of special particle swarm optimization (PSO) algorithm is proposed that successfully combines the classic genetic algorithm (GA), and greatly improves its own search capability. Second, a pretreatment strategy is put forward to deal with obstacles and pins, which can provide a fast information inquiry for the whole algorithm by generating a precomputed lookup table. Third, we present an efficient adjustment method, which enables particles to avoid all the obstacles by introducing some corner points of obstacles. Finally, an excellent refinement method is discussed to further enhance the quality of the final routing tree, which can improve the quality of the solution by 7.93% on average. To our best knowledge, this is the first time to specially solve the single-layer obstacle-avoiding problem in X-architecture. Experimental results show that the proposed algorithm can further shorten wirelength in the presence of obstacles. And it achieves the best solution quality in a reasonable runtime among the existing algorithms.

The class Steiner minimal tree problem is an extension of the standard Steiner minimal tree problem in graphs, motivated by the problem of wire routing in the area of physical design of very large scale integration (VLSI). This problem is NP-hard, even if there are no Steiner nodes and the graph is a tree; moreover, there exists no polynomial time approximation algorithm with a constant bound on the relative error under the hypothesis that P \(\neq\) NP [16]. Hence, fast and good heuristic algorithms are needed in practice. In this paper, we present an integer programming formulation of the problem. Using Lagrangean relaxation and subgradient optimization, we derive a lower bound. In order to test the lower bound, we present a procedure for generating test problems for the class Steiner minimal tree problem that have known optimal solutions. The computational experiments for the test problems demonstrate that the lower bound is very tight and differs from the optimal solutions by only a few percent on average for sparse graphs.

The switchbox rectilinear Steiner tree problem, which is to construct an optimal rectilinear Steiner tree interconnecting n terminals on the perimeter of a switchbox without crossing any obstacles inside the switchbox, is addressed. An algorithm that computes an optimal switchbox rectilinear Steiner tree in O(F/sub 1/(k)n+F/sub 2/(k)) time, where k is the number of obstacles inside the switchbox and F/sub 1/ and F/sub 2/ are exponential functions of k, is presented. For any constant k, the proposed algorithm runs in O(n) time. As an immediate extension, it is possible to generate m Steiner trees in O(mn) time and select the best one among them. >

In the paper, we provide a timing-driven rectilinear routing tree algorithm which applies top-down partitioning followed by the bottom-up routing tree construction in the presence of the obstacles. The objective is to simultaneously minimize the source-to-terminal delay and the total wirelength. First, a top-down partitioning method is used to divide the chip into four sub-regions according to the position of the source. Then, the terminals in each sub-region are connected by a fast sequential routing tree algorithm. The major steps of the routing algorithm include minimal spanning tree constructing, invalid edges pushing and routing. It shows experimentally that the maximum source-to-terminal delay of the routing tree is improved by 74%. Compared to previous results, total wirelength is significantly reduced by 34.7%.

We investigate the role convexity plays in the efficient solution to the Steiner tree problem. In general terms, we show that a Steiner tree problem is always computationally easier to solve when the points to be connected lie on the boundary of a “convex” region. For the Steiner tree problem on graphs and the rectilinear Steiner tree problem, we give definitions of “convexity” for which this condition is sufficient to allow a polynomial algorithm for finding the optimal Steiner tree. For the classical Steiner tree problem, we show that for the standard definition of convexity, this condition is sufficient to allow a fully polynomial approximation scheme.

: This report describes techniques for very large scale integration (VLSI) implementation of arithmetic algorithms. The report describes an algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root. Keywords include: Very large scale integration (VLSI); and Floating point chip design.

This paper presents a new model for VLSI routing in the presence of obstacles and boundary. A new approach for reduction of the routing area is proposed, and a modified Lee algorithm - weighted Lee algorithm is applied on the extended Hanan grid to compute sub-optimal RSMT in $O(n^2(n+m)^2\log(n+m))$ time, where $n$ is the number of terminals, $m$ is the number of vertices of obstacles and boundary.

Rectilinear Steiner spanning trees are used in several phases of the VLSI physical design process when collections of terminals must be connected to a common electrical point. The authors present a new linear time heuristic algorithm for generating these rectilinear Steiner trees. They begin with minimal spanning trees and transform those configurations which are never found in the shortest Steiner trees. This decreases the length of the spanning trees. In addition to its speed, the algorithm is straightforward and can be implemented efficiently. Empirical results demonstrate that reductions of over 13% in length are possible, while an average of over 8% reduction is achieved. This compares very favorably to much more complex algorithms. The algorithm is recommended for applications where many spanning trees are needed in a very short time. >

We present a chip-level global router based on a new, more accurate global routing model for the multilayer macro-cell (building block) technology. The routing model uses a three-dimensional mixed directed/undirected routing graph, which provides not only the topological information but also the layer information. The irregular routing graph closely models the multilayer routing problem, so the global router can give an accurate estimate of the routing resources needed. Route-searching is formulated as the Steiner problem in networks (graph Steiner tree problem). Although the Steiner problem in networks is an NP-hard problem, it can generate better routes than other approaches. Previously published Steiner tree heuristics can not handle the complexity of the modern routing graphs. We developed an improved Steiner tree heuristic algorithm which can take advantage of the features of routing graphs. Tested on industrial circuits, our algorithm yields comparable results while having dramatically lower time and space complexities than the leading heuristics. The efficiency and effectiveness of our algorithm make our global router applicable to large industrial circuits, easily handling multilayer problems consisting of 200 macro cells and 10000 nets. While minimizing the wire length, our global router can also minimize the number of vias or solve the routing resource congestion problems.

We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuously analyzing the congestion at all steps, nets are incrementally globally routed in one of the six well thought of heuristic steps of our methodology. This eliminates the need for rip-up and re-route and enables our approach to achieve good completion rates. We tested our flow on a number of testcases from the industry. The net lengths produced by our flow were compared to the theoretical lower-bound (steiner tree) and were found to be at most 4% worse. We compared the results of creating the net segments by the classical MST verses the CDST and observed an 80% improvement in the number of incomplete nets. Completing the detailed routing using a commercially available detailed router validated the results of the proposed global routing and cross-point assignment.