An algorithm for exact rectilinear Steiner trees for switchbox with obstacles

The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NP-hard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST heuristics is the Batched Iterated 1-Steiner (BI1S) heuristic of Kahng and Robins (1992). In a recent development, exact RST algorithms have witnessed spectacular progress: the new release of the GeoSteiner code of Warme, Winter, and Zachariasen (1998) has average running time comparable to that of the fastest available Bl1S implementation, due to Robins. We are thus faced with the paradoxical situation that an exact algorithm for an NP-hard problem is competitive in speed with a state-of-the-art heuristic for the problem. The main contribution of this paper is a new RST heuristic, which has at its core a recent 3/2 approximation algorithm of Rajagopalan and Vazirani (1999) for the metric Steiner tree problem on quasi-bipartite graphs-these are graphs that do not contain edges connecting pairs of Steiner vertices. The RV algorithm is built around the linear programming relaxation of a sophisticated integer program formulation, called the bidirected cut relaxation. Our heuristic achieves a good running time by combining an efficient implementation of the RV algorithm with simple, but powerful geometric reductions. Experiments conducted on both random and real VLSI instances show that the new RST heuristic runs significantly faster than Robins' implementation of BI1S and than the GeoSteiner code. Moreover, the new heuristic typically gives higher-quality solutions than Bl1S.

A rectilinear Steiner tree for a set T of points in the plane is a tree which connects T using horizontal and vertical lines. In the Rectilinear Steiner Tree problem, input is a set T of n points in the Euclidean plane (R^2) and the goal is to find an rectilinear Steiner tree for T of smallest possible total length. A rectilinear Steiner arborecence for a set T of points and root r in T is a rectilinear Steiner tree S for T such that the path in S from r to any point t in T is a shortest path. In the Rectilinear Steiner Arborescense problem the input is a set T of n points in R^2, and a root r in T, the task is to find an rectilinear Steiner arborescence for T, rooted at r of smallest possible total length. In this paper, we give the first subexponential time algorithms for both problems. Our algorithms are deterministic and run in 2^{O(sqrt{n}log n)} time.

We consider the problem of finding a shortest rectilinear Steiner tree for a given set of points in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if we intersect the Steiner tree with some obstacle, then no connected component of the induced subtree must be longer than a given fixed length L. This kind of length restriction is motivated by its application in VLSI design where a large Steiner tree requires the insertion of buffers (or inverters) which must not be placed on top of obstacles. We show that the length-restricted Steiner tree problem can be approximated with a performance guarantee of 2 in O(n logn) time, where n denotes the size of the associated Hanan grid. Optimal length-restricted Steiner trees can be characterized to have a special structure. In particular, we prove that a certain graph, which is a variant of the Hanan grid, always contains an optimal solution. Based on this structural result, we can improve the performance guarantee of approximation algorithms for the special case that all obstacles are of rectangular shape or of constant complexity, i.e. they are represented by at most a constant number of edges. For such a scenario, we give a $\frac{5}{4}\alpha$ -approximation and a $\frac{2k}{2k-1}\alpha$ -approximation for any integral k ≥ 4, where α denotes the performance guarantee for the ordinary Steiner tree problem in graphs.

The Steiner tree problem is one of the fundamental optimization problems in distributed graph algorithms. Recently Saikia and Karmakar [27] proposed a deterministic distributed algorithm for the Steiner tree problem that constructs a Steiner tree in \(O(S + \sqrt{n} \log ^* n)\) rounds whose cost is optimal upto a factor of \(2(1 - 1/\ell )\), where n and S are the number of nodes and shortest path diameter [17] respectively of the given input graph and \(\ell \) is the number of terminal leaf nodes in the optimal Steiner tree. The message complexity of the algorithm is \(O(\varDelta (n - t) S + n^{3/2})\), which is equivalent to \(O(mS + n^{3/2})\), where \(\varDelta \) is the maximum degree of a vertex in the graph, t is the number of terminal nodes (we assume that \(t < n\)), and m is the number of edges in the given input graph. This algorithm has a better round complexity than the previous best algorithm for Steiner tree construction due to Lenzen and Patt-Shamir [21]. In this paper we present a deterministic distributed algorithm which constructs a Steiner tree in \(\tilde{O}(S + \sqrt{n})\) rounds and \(\tilde{O}(mS)\) messages and still achieves an approximation factor of \(2(1 - 1/\ell )\). Note here that \(\tilde{O}(\cdot )\) notation hides polylogarithmic factors in n. This algorithm improves the message complexity of Saikia and Karmakar’s algorithm by dropping the additive term of \(O(n^{3/2})\) at the expense of a logarithmic multiplicative factor in the round complexity. Furthermore, we show that for sufficiently small values of the shortest path diameter \((S=O(\log n))\), a \(2(1 - 1/\ell )\)-approximate Steiner tree can be computed in \(\tilde{O}(\sqrt{n})\) rounds and \(\tilde{O}(m)\) messages and these complexities almost coincide with the results of some of the singularly-optimal minimum spanning tree (MST) algorithms proposed in [9, 12, 23].

We investigate the role convexity plays in the efficient solution to the Steiner tree problem. In general terms, we show that a Steiner tree problem is always computationally easier to solve when the points to be connected lie on the boundary of a “convex” region. For the Steiner tree problem on graphs and the rectilinear Steiner tree problem, we give definitions of “convexity” for which this condition is sufficient to allow a polynomial algorithm for finding the optimal Steiner tree. For the classical Steiner tree problem, we show that for the standard definition of convexity, this condition is sufficient to allow a fully polynomial approximation scheme.

Very large scale integration (VLSI) global routing is typically performed on a rectangular die space amidst multiple IP cores and gates, typically treated as obstacles during net routing. In this paper, we address the global routing problem of a multi-terminal net in presence of obstacles, and name it as Obstacle-avoiding Group Steiner tree (OAGST) construction. The proposed method comprises of the following procedures. Given a number of obstacles, and pins (terminals) on a die, (1) first empty rectangular regions, called maximal empty rectangles, are constructed avoiding obstacles. (2) Next, a split - and - merge technique is adopted to regenerate L-shaped rectilinear regions over the maximal empty rectangles. Partial Rectilinear Steiner tree (RST) is constructed from each L-shaped region by routing the pin terminals inside the region. (3)The split - and - merged regions are next converted to a dual graph following neighbouring corner-stich method. Finally, a complete Obstacle-avoiding Group Steiner tree/Rectilinear Steiner tree is constructed from the dual graph by redundant edge deletion. A comparative study of our algorithm with an existing work shows improvement in many cases.

The rectilinear Steiner tree (RST) problem is known to be $NP$-complete for an arbitrary set of points in the plane. In this paper we extend the known cases for which solutions can be determined in linear time to include sets of points which generate types of minimum-distance rectangle trees. Rectangle trees are rectilinear, plane $C_4 $-trees. A minimum-distance rectangle tree is a rectangle tree such that the length of a shortest path between any two vertices in the graph is equal to the rectilinear distance (in the plane) between the two vertices. A complete enumeration of minimum-distance rectangle trees is included. The results have application in the design of terminal patterns and wiring layouts for electronic circuitry.

A super-stabilizing [formula omitted]-approximation algorithm for dynamic Steiner trees

Rectilinear Steiner spanning trees are used in several phases of the VLSI physical design process when collections of terminals must be connected to a common electrical point. The authors present a new linear time heuristic algorithm for generating these rectilinear Steiner trees. They begin with minimal spanning trees and transform those configurations which are never found in the shortest Steiner trees. This decreases the length of the spanning trees. In addition to its speed, the algorithm is straightforward and can be implemented efficiently. Empirical results demonstrate that reductions of over 13% in length are possible, while an average of over 8% reduction is achieved. This compares very favorably to much more complex algorithms. The algorithm is recommended for applications where many spanning trees are needed in a very short time. >

The following problems are worth studying: Open problems on the Steiner ratio, such as Chung-Gilbert’s conjecture, Graham-Hwang’s conjecture, and Cielick’s conjecture, etc.. Find better approximation for network Steiner trees and establish an explicit lower bound for the approximation performance ratio of network Steiner trees. Close the gap between the lower bound and the upper bound for the approximation performance ratio of Steiner minimum arborescence. Find more efficient approximation algorithms for on-line and dynamic Steiner minimum trees and various Steiner tree packing problems. Find good approximation algorithms for multi-weighted Steiner trees and multiphase Steiner trees and study close relationship between multi-weighted Steiner trees, multiphase Steiner trees, and phylogenetic trees. Make clear whether there exists a polynomial-time approximation scheme for class Steiner tree in the special case with the real world background and highway interconnection problem. Close the gap between the lower bound and the upper bound for the approximation performance ratio of bottleneck Steiner tree in the Euclidean plane and make clear whether there exists a polynomial-time approximation scheme for the Steiner tree with minimum number of Steiner points and bounded edge-length. Implement efficient approximation algorithms to meet the requests from industries.

An optimum rectilinear Steiner tree for a set A of points in the plane is a tree which interconnects A using horizontal and vertical lines of shortest possible total length. Such trees correspond to single net wiring patterns on printed backplanes which minimize total wire length. We show that the problem of determining this minimum length, given A, is $NP$-complete. Thus the problem of finding optimum rectilinear Steiner trees is probably computationally hopeless, and the emphasis of the literature for this problem on heuristics and special case algorithms is well justified. A number of intermediary lemmas concerning the $NP$-completeness of certain graph-theoretic problems are proved and may be of independent interest.

During the physical design process, prior to detailed routing, it is desired to bound the interconnect delay based on the bounding box of the pins on the net, horizontal, and vertical estimates of interconnect capacitance and resistance per length and estimate the pin-to-pin delays based on the positions of the pins inside and on the bounding box. Assuming the interconnect will be routed based on a rectilinear Steiner tree (RST), the work of F.K. Chung and F.H. Hwang (1979) is used to bound the size of the largest and smallest possible RSTs given the bounding-box of the pins on the net (this is done for nets with >

This paper considers the problem of synthesizing application-specific network-on-chip (NoC) architectures. We propose two heuristic algorithms called CLUSTER and DECOMPOSE that can systematically examine different set partitions of communication flows, and we propose Rectilinear-Steiner-tree (RST) based algorithms for generating an efficient network topology for each group in the partition. Different evaluation functions in fitting with the implementation backend and the corresponding implementation technology can be incorporated into our solution framework to evaluate the implementation cost of the set partitions and RST topologies generated. In particular, we experimented with an implementation cost model based on the power consumption parameters of a 70 nm process technology where leakage power is a major source of energy consumption. Experimental results on a variety of NoC benchmarks showed that our synthesis results can on average achieve a 6.92 x reduction in power consumption over the best standard mesh implementation. To further gauge the effectiveness of our heuristic algorithms, we also implemented an exact algorithm that enumerates all distinct set partitions. For the benchmarks where exact results could be obtained, our CLUSTER and DECOMPOSE algorithms on average can achieve results within 1% and 2% of exact results, with execution times all under 1 second whereas the exact algorithms took as much as 4.5 hours.

The rectilinear Steiner tree problem asks for a shortest network connecting n terminals in the rectilinear plane (with L1‐metric). The problem can be considered as a special case of the Steiner tree problem in a grid network obtained by drawing horizontal and vertical lines through terminals. The reductions developed for the network variant of the Steiner tree problem can therefore also be used in the rectilinear case. However, computational experience indicates that they are not very powerful in the rectilinear grids. We introduce a limited number of rectilinear reductions based on the geometrical properties of terminals. Experimental results show that these reductions are extremely powerful while being quite simple to verify and easy to implement. For randomly generated problem instances with one terminal per row and column, The number of nonterminals remaining seems to be around 20‐‐25% of their original number. Furthermore, The performance of geometrical reductions improves as the density of terminals in fixed‐size grids grows.

The most crucial factor that degrades a high speed VLSI is the signal propagation delay in a routing tree. It is estimated additively by the amount of the source-to-sink path length and total length. To design a routing tree in which these two are balancingly small, we propose an algorithm to construct a spanning tree, by which a tree is constructed in a hybrid way of the Minimum-Tree and Shortest-Path Tree algorithms. The idea is extended to finding such a rectilinear Steiner tree. Experiments are given to show how the source-to-sink path length and total length are balanced and small.