Cost-radius balanced spanning/Steiner trees

A rectilinear Steiner tree for a set T of points in the plane is a tree which connects T using horizontal and vertical lines. In the Rectilinear Steiner Tree problem, input is a set T of n points in the Euclidean plane (R^2) and the goal is to find an rectilinear Steiner tree for T of smallest possible total length. A rectilinear Steiner arborecence for a set T of points and root r in T is a rectilinear Steiner tree S for T such that the path in S from r to any point t in T is a shortest path. In the Rectilinear Steiner Arborescense problem the input is a set T of n points in R^2, and a root r in T, the task is to find an rectilinear Steiner arborescence for T, rooted at r of smallest possible total length. In this paper, we give the first subexponential time algorithms for both problems. Our algorithms are deterministic and run in 2^{O(sqrt{n}log n)} time.

An optimum rectilinear Steiner tree for a set A of points in the plane is a tree which interconnects A using horizontal and vertical lines of shortest possible total length. Such trees correspond to single net wiring patterns on printed backplanes which minimize total wire length. We show that the problem of determining this minimum length, given A, is $NP$-complete. Thus the problem of finding optimum rectilinear Steiner trees is probably computationally hopeless, and the emphasis of the literature for this problem on heuristics and special case algorithms is well justified. A number of intermediary lemmas concerning the $NP$-completeness of certain graph-theoretic problems are proved and may be of independent interest.

As devices and lines shrink into the deep submicron range, the propagation delay of signals can be effectively improved by repowering the signals using intermediate buffers placed within the routing trees. Almost no existing timing driven floorplanning and placement approaches consider the option of buffer insertion. As such, they may exclude solutions, particularly early in the design process, with smaller overall area and better routability. In this paper, we propose a new methodology in which buffered trees are used to estimate wire delay during floorplanning. Instead of treating delay as one of the objectives, as done by the majority of previous work, we formulate the problem in terms of delay bounded buffered trees (DBB-tree) and propose an efficient algorithm to construct a DBB spanning tree for use during floorplanning. Experimental results show that the algorithm is very effective. Using buffer insertion at the floorplanning stage yields significantly better solutions in terms of both chip area and total wire length.

The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NP-hard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST heuristics is the Batched Iterated 1-Steiner (BI1S) heuristic of Kahng and Robins (1992). In a recent development, exact RST algorithms have witnessed spectacular progress: the new release of the GeoSteiner code of Warme, Winter, and Zachariasen (1998) has average running time comparable to that of the fastest available Bl1S implementation, due to Robins. We are thus faced with the paradoxical situation that an exact algorithm for an NP-hard problem is competitive in speed with a state-of-the-art heuristic for the problem. The main contribution of this paper is a new RST heuristic, which has at its core a recent 3/2 approximation algorithm of Rajagopalan and Vazirani (1999) for the metric Steiner tree problem on quasi-bipartite graphs-these are graphs that do not contain edges connecting pairs of Steiner vertices. The RV algorithm is built around the linear programming relaxation of a sophisticated integer program formulation, called the bidirected cut relaxation. Our heuristic achieves a good running time by combining an efficient implementation of the RV algorithm with simple, but powerful geometric reductions. Experiments conducted on both random and real VLSI instances show that the new RST heuristic runs significantly faster than Robins' implementation of BI1S and than the GeoSteiner code. Moreover, the new heuristic typically gives higher-quality solutions than Bl1S.

The switchbox rectilinear Steiner tree problem, which is to construct an optimal rectilinear Steiner tree interconnecting n terminals on the perimeter of a switchbox without crossing any obstacles inside the switchbox, is addressed. An algorithm that computes an optimal switchbox rectilinear Steiner tree in O(F/sub 1/(k)n+F/sub 2/(k)) time, where k is the number of obstacles inside the switchbox and F/sub 1/ and F/sub 2/ are exponential functions of k, is presented. For any constant k, the proposed algorithm runs in O(n) time. As an immediate extension, it is possible to generate m Steiner trees in O(mn) time and select the best one among them. >

The rectilinear Steiner tree (RST) problem is known to be $NP$-complete for an arbitrary set of points in the plane. In this paper we extend the known cases for which solutions can be determined in linear time to include sets of points which generate types of minimum-distance rectangle trees. Rectangle trees are rectilinear, plane $C_4 $-trees. A minimum-distance rectangle tree is a rectangle tree such that the length of a shortest path between any two vertices in the graph is equal to the rectilinear distance (in the plane) between the two vertices. A complete enumeration of minimum-distance rectangle trees is included. The results have application in the design of terminal patterns and wiring layouts for electronic circuitry.

We consider the problem of finding a shortest rectilinear Steiner tree for a given set of points in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if we intersect the Steiner tree with some obstacle, then no connected component of the induced subtree must be longer than a given fixed length L. This kind of length restriction is motivated by its application in VLSI design where a large Steiner tree requires the insertion of buffers (or inverters) which must not be placed on top of obstacles. We show that the length-restricted Steiner tree problem can be approximated with a performance guarantee of 2 in O(n logn) time, where n denotes the size of the associated Hanan grid. Optimal length-restricted Steiner trees can be characterized to have a special structure. In particular, we prove that a certain graph, which is a variant of the Hanan grid, always contains an optimal solution. Based on this structural result, we can improve the performance guarantee of approximation algorithms for the special case that all obstacles are of rectangular shape or of constant complexity, i.e. they are represented by at most a constant number of edges. For such a scenario, we give a $\frac{5}{4}\alpha$ -approximation and a $\frac{2k}{2k-1}\alpha$ -approximation for any integral k ≥ 4, where α denotes the performance guarantee for the ordinary Steiner tree problem in graphs.

During the physical design process, prior to detailed routing, it is desired to bound the interconnect delay based on the bounding box of the pins on the net, horizontal, and vertical estimates of interconnect capacitance and resistance per length and estimate the pin-to-pin delays based on the positions of the pins inside and on the bounding box. Assuming the interconnect will be routed based on a rectilinear Steiner tree (RST), the work of F.K. Chung and F.H. Hwang (1979) is used to bound the size of the largest and smallest possible RSTs given the bounding-box of the pins on the net (this is done for nets with >

We consider t-ary trees characterized by their numbers of nodes and their total path length. When t=2 these are called binary trees, and in such trees a parent node may have up to t child nodes. We give asymptotic expansions for the total number of trees with nodes and path length p, when n and p are large. We consider several different ranges of n and p. For n→∞ and p=O(n^{3/2}) we recover the Airy distribution for the path length in trees with many nodes, and also obtain higher order asymptotic results. For p→∞ and an appropriate range of n we obtain a limiting Gaussian distribution for the number of nodes in trees with large path lengths. The mean and variance are expressed in terms of the maximal root of the Airy function. Singular perturbation methods, such as asymptotic matching and WKB type expansions, are used throughout, and they are combined with more standard methods of analytic combinatorics, such as generating functions, singularity analysis, saddle point method, etc. The results are applicable to problems in information theory, that involve data compression schemes which parse long sequence into shorter phrases. Numerical studies show the accuracy of the various asymptotic approximations. Key Words: Trees; Universal Types; Asymptotics; Path Length; Singular Perturbations

A Wireless Sensor Network (WSN) is a network comprised of sensor nodes and a designated device called a sink to which nodes transmit their sensed data. Nodes are low-cost, battery-powered devices with limited memory and computational power. Usually WSNs are deployed with a single sink and left unattended for a long time. During this time sensor nodes, communication links between the nodes, and the sink may go down or crash due to energy depletion, harsh environment, or for some other reasons. If the sink crashes, then the network becomes useless as the sink will not be able to collect data from nodes. One way of making the network more reliable is to deploy networks with more than one sink. Existing efficient data aggregation protocols developed for WSNs with a single sink may not show the similar efficiency in WSNs with multiple sinks. In this paper, we first define the data aggregation problem in WSNs with multiple sinks, and then propose two data aggregation algorithms for a WSN with multiple sinks that minimize the number of data packet transmissions during data collection. The first one is based on a Minimum Spanning Tree algorithm and the second one is based on a Shortest Path Tree algorithm. Simulation results show the effectiveness of the proposed algorithms.

The performance of high speed computers depends not only on IC chips, but also on the signal propagation speed between these chips. The signal propagation delay in a computer is determined by the dielectric constant of the substrate material to which the IC chips are attached. In this study, a ceramic substrate with a low dielectric constant (k ≈ 5.0) has been developed. When compared with the traditional alumina substrate (k ≈ 10.0), the new material corresponds to a 37% decrease in the signal propagation delay. Glass hollow spheres are used to introduce porosity (k = 1.0) to the alumina matrix in a controlled manner. A surface coating technique via heterogeneous nucleation in aqueous solution has been used to improve the high temperature stability of these spheres. After sintering at 1,400 C, isolated spherical pores are uniformly distributed in the almost fully dense alumina matrix; negligible amounts of matrix defects can be seen. All pores are isolated from each other. Detailed analyses of the chemical composition find that the sintered sample consists of α-alumina, mullite and residual glass. Mullite is the chemical reaction product of alumina and the glass spheres. Residual glass exists because current firing conditions do not complete the mullitization reaction. The dielectric constant of the sintered sample is measured and then compared with the predicted value using Maxwell`s model. Mechanical strength is evaluated by a four-point bending test. Although the flexural strength decreases exponentially with porosity, samples with 34% porosity (k ≈ 5.0) still maintain adequate mechanical strength for the proper operation of a microelectronic substrate.

Very large scale integration (VLSI) global routing is typically performed on a rectangular die space amidst multiple IP cores and gates, typically treated as obstacles during net routing. In this paper, we address the global routing problem of a multi-terminal net in presence of obstacles, and name it as Obstacle-avoiding Group Steiner tree (OAGST) construction. The proposed method comprises of the following procedures. Given a number of obstacles, and pins (terminals) on a die, (1) first empty rectangular regions, called maximal empty rectangles, are constructed avoiding obstacles. (2) Next, a split - and - merge technique is adopted to regenerate L-shaped rectilinear regions over the maximal empty rectangles. Partial Rectilinear Steiner tree (RST) is constructed from each L-shaped region by routing the pin terminals inside the region. (3)The split - and - merged regions are next converted to a dual graph following neighbouring corner-stich method. Finally, a complete Obstacle-avoiding Group Steiner tree/Rectilinear Steiner tree is constructed from the dual graph by redundant edge deletion. A comparative study of our algorithm with an existing work shows improvement in many cases.

Video motion analysis (VMA) uses fluoroscopic sequences to derive catheter and guidewire movement, and is able to calculate 2D catheter-tip path length (PL) on the basis of frame-by-frame pixel coordinates. The objective of this study was to validate VMA in coronary angiography as a method of skill assessment. Forty-seven coronary interventions performed by 10 low- (<1,000 cases; group A), five medium- (1,000-4,000; group B) and six high- (>4,000; group C) experience-volume cardiologists were prospectively recorded and analysed using VMA software. Total PL was calculated and procedure, fluoroscopy times, and radiation dose were recorded. Comparisons of PL were made between groups of experience. Groups A, B and C performed 24, 14 and 6 paired (right and left coronary) cannulations, respectively. Calculation of PL was possible in all recorded cases and significantly correlated with procedure (p=<0.001, rho=0.827) and fluoroscopy times (p=<0.001, rho=0.888). Median total path length (combined right and left coronaries) was significantly shorter in group C which used 3,836 pixels of movement (IQR: 3,003-4,484) vs. 10,556 (7,242-31,408) in group A (p=<0.001) and 8,725 (5,187-15,150) in group B (p=0.013). VMA in coronary angiography is feasible and PL is able to differentiate levels of experience.

Rectilinear Steiner spanning trees are used in several phases of the VLSI physical design process when collections of terminals must be connected to a common electrical point. The authors present a new linear time heuristic algorithm for generating these rectilinear Steiner trees. They begin with minimal spanning trees and transform those configurations which are never found in the shortest Steiner trees. This decreases the length of the spanning trees. In addition to its speed, the algorithm is straightforward and can be implemented efficiently. Empirical results demonstrate that reductions of over 13% in length are possible, while an average of over 8% reduction is achieved. This compares very favorably to much more complex algorithms. The algorithm is recommended for applications where many spanning trees are needed in a very short time. >

Underwater Wireless Sensor Networks (UWSNs) are getting growing interest because of wide-range of applications. Most applications of these networks demand reliable data delivery over longer period in an efficient and timely manner. However, resource-constrained nature of these networks makes routing in a harsh and unpredictable underwater environment challenging. Most existing schemes either employ static or mobile sink for data collection. However, in former sensors near the sink deplete out their energy more quickly which limits network lifetime. Mobile sink based schemes are not suitable for delay-sensitive large-scale applications. Unlike prior work, this paper presents a novel Advanced AUV-aided Energy Efficient Routing Protocol (AAEERP) for reliable data delivery. To prolong network lifetime, AAEERP employs an autonomous underwater vehicle to collect data from gateways. To minimize energy consumption, we use a shortest path tree algorithm while associating sensor nodes with the gateways and devise a criterion to limit the association count of nodes. Moreover, the role of gateways is rotated to balance the energy consumption. To prevent data loss, AAEERP allows dynamic data collection time to AUV depending up the count of member sensors for each gateway. The performance of the AAEERP is validated through simulations. Simulation results demonstrate the effectiveness of AAEERP in terms of various performance metrics.