Delay bounded buffered tree construction for timing driven floorplanning

The most crucial factor that degrades a high speed VLSI is the signal propagation delay in a routing tree. It is estimated additively by the amount of the source-to-sink path length and total length. To design a routing tree in which these two are balancingly small, we propose an algorithm to construct a spanning tree, by which a tree is constructed in a hybrid way of the Minimum-Tree and Shortest-Path Tree algorithms. The idea is extended to finding such a rectilinear Steiner tree. Experiments are given to show how the source-to-sink path length and total length are balanced and small.

The first stage in channel routing is that of computing a routing solution S, for a given channel with as few tracks as possible. We consider a second stage in which it is desirable to reduce the total wire length without increasing area of routing. In this paper we propose efficient polynomial time algorithms for appreciably reducing the total wire length in two-, three- and multi-layer routing solutions by permuting tracks in the solution S obtained in the first stage. This results in a routing solution that is economical in terms of area as well as total wire length. Our algorithms are particularly important in practical terms since the problem of minimizing the total wire length in a routing solution is NP-hard.

In the paper, we provide a timing-driven rectilinear routing tree algorithm which applies top-down partitioning followed by the bottom-up routing tree construction in the presence of the obstacles. The objective is to simultaneously minimize the source-to-terminal delay and the total wirelength. First, a top-down partitioning method is used to divide the chip into four sub-regions according to the position of the source. Then, the terminals in each sub-region are connected by a fast sequential routing tree algorithm. The major steps of the routing algorithm include minimal spanning tree constructing, invalid edges pushing and routing. It shows experimentally that the maximum source-to-terminal delay of the routing tree is improved by 74%. Compared to previous results, total wirelength is significantly reduced by 34.7%.

Buffer insertion and wire sizing are critical in deep submicron VLSI design. This paper studies the problem of constructing routing trees with simultaneous buffer insertion and wire sizing in the presence of routing and buffer obstacles. No previous algorithms consider all these factors simultaneously. Previous dynamic programming based algorithm is first extended to solve the problem. However, with the size of routing graph increasing and with wire sizing taken into account, the time and space requirement increases enormously. Then a new approach is proposed to formulate the problem as a series of graph problems. The routing tree solution is obtained by finding shortest paths in a series of graphs. In the new approach, wire sizing can be handled almost without any additional time and space requirement, Moreover, the time and space requirement is only polynomial in terms of the size of routing graph. Our algorithm differs from traditional dynamic programming, and is capable of addressing the problem of inverter insertion and sink polarity. Both theoretical and experimental results show that the graph-based algorithm outperforms the DP-based algorithm by a large margin. We also propose a hierarchical approach to construct routing tree for a large number of sinks.

In the routing design of interposer and etc., the combination of a pin pair to be connected by wire is often flexible, and the reductions of the total wire length and the length difference are pursued to keep the circuit performance. Even though the total wire length can be minimized by finding a minimum cost maximum flow in set pair routing problems, the length difference is often large, and the reduction of it is not easy. In this paper, an algorithm that reduces the length difference while keeping the total wire length small is proposed. In the proposed algorithm, an initial routing first obtained by a minimum cost maximum flow. Then it is modified to reduce the maximum length while keeping the minimum total wire length, and a connection of the minimum length is detoured to reduce the length difference. The effectiveness of the proposed algorithm is confirmed by experiments.

In this paper, we propose a new quick and effective legitimate skew clock routing with buffer insertion algorithm. We analyze the optimal buffer position in the clock path, and conclude the sufficient condition and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates buffer insertion and node merging together, and performs them in parallel. Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%. Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay. The experimental results show that our algorithm is quick and effective.

With shrinking VLSI feature sizes and increasing overall chip areas, buffering has emerged as an effective solution to the problem of growing interconnect delays in modern designs. The problem of buffer insertion in a single net has been the focus of most previous researches. However, efficient algorithms for buffer insertion in whole circuits are generally needed. In this paper, we relate the timing constrained minimal buffer insertion problem to the min-cost flow dual problem, and propose two algorithms based on min-cost flow and min-cut techniques, respectively, to solve it in combinational circuits. We compare our approaches to a traditional approach based on Lagrangian relaxation. Experimental results demonstrate that our approaches are efficient and effective. On the average, our approaches achieve 45% and 39% reduction, respectively, on the number of buffers inserted in comparison to the traditional approach.

Consider a set of n pins and $n( n - 1 )/2$ specified numbers of wire connections between all pairs of the n pins There are also n holes all in a line with adjacent holes at unit distances apart. The problem is to put the n pins into the n holes such that the total wire length is a minimum. We can abstract the pins and wire connections as a graph G with n nodes and numbers associated with the arcs. For an arbitrary G, we establish a lower bound on the total wire length. If G is a rooted tree, an algorithm is presented which requires $O( {n\log n} )$ operations.

Koch fractal monopole antennas are known to exhibit lower resonant frequencies than Euclidean monopoles of the same height. It has been concluded that there exists a unique relationship between the antenna's fractal geometry and its electromagnetic behavior. Here, the performance properties of the Koch fractal monopole are examined and compared with the performance properties of other bent wire geometry monopoles having the same total wire length and overall height. It is demonstrated that monopoles with less complex shapes exhibit lower resonant frequencies because they are more effective at increasing the electrical volume of the antenna. When these antennas are made to be resonant at the same frequency, they exhibit virtually identical performance properties independent of differences in their geometric shape and total wire length. It is also demonstrated that the effective height of these monopoles converge to that of an electrically small Euclidean monopole near the small antenna limit and they exhibit virtually identical radiation resistance properties at low frequencies. Finally, it is shown that the fractal limit in lowering of resonant frequency is related to the limit in the increase in the antenna's effective volume.

The resonant properties of several small planar space-filling fractal antennas are considered over a range of self-resonant frequencies. These space-filling antennas have differing geometries and total wire length, but occupy the same planar area. The resonant properties considered include radiation resistance, efficiency, and quality factor. It is demonstrated that the resonant properties of these antennas are essentially the same, independent of significant differences in antenna geometry and total wire length.

Channel routing problem of area minimization is a well-defined problem in VLSI physical design automation. In this paper we have developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions. Here we consider the total wire length of a routing solution as one of the most important factors of high performance computing. Reduction in wire length is important from signal delay as well as from the viewpoint of cost of wire segments required in interconnecting all the nets. The framework is designed for computing routing solutions in two-layer channels, and extended to route three-layer routing also in a modular fashion. All the algorithms developed under the framework of TAH are executed for computing no-dogleg and dogleg routing solutions for most of the well-known benchmark channels, with reduced total area and/or total wire length in two- and three-layer channel routing. Performance of our algorithms is highly encouraging.

In this paper, we propose new approaches for solving the useful-skew tree (UST) routing problem [17]: Clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for zero-skew tree [5; 1] and bounded-skew tree [8; 2] routings; hence, the names UST/DME and Greedy-UST/DME for our algorithms. They simultaneously perform skew scheduling and tree routing such that each local skew range is incrementally refined to a skew value that minimizes the wirelength during the bottom-up merging phase of DME. The resulting skew schedule is not only feasible, but is also best for routing in terms of wirelength. The experimental results show very encouraging improvement over the previous BST/DME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total wirelength.

We previously used back propagation neural network (BPNN) with the meteorological factors of the receiver point to establish a model for predicting propagation delay of Loran-C signal over a short distance. Nevertheless, for a long propagation path, it is not proper to use only the meteorological factors of the receiver point. In this letter, a propagation delay prediction model that considers multiweather and multipoint was established by using a more suitable generalized regression neural network (GRNN) over a long distance. We first compared three meteorological factors of six points on the propagation path, and found that they have obvious differences. Then, a propagation delay prediction model based on three meteorological factors of the six points is established with GRNN. Finally, the further comparison shows that on the one hand, GRNN is more suitable to establish the prediction model of propagation delay than BPNN; on the other hand, more points on the propagation path are considered, and the prediction accuracy of the model is higher.

The quality of the clock distribution networks (CDNs) impacts the performance of an SoC. In this paper, we propose local topology modification (LTM) in order to enhance the CDN's quality in terms of total wire length and wire elongations. The incorporation of this method into a deferred-merge embedding algorithm (DME) and greedy-DME (GDME) reduces the total wire length by around 7.83% and 9.77% respectively, with a slight increase in run time. In addition, we show that GDME relies intensively on wire elongations and it offers a solution that suffers from high standard deviation of the path lengths between clock pins and the CDN's root (SDPL). Applying LTM to GDME reduces wire elongations and SDPL by 96.4 % and 51.5 % respectively.

In this paper we describe the Fixed-points Addition and Relaxation(FAR) based placement technique. Fixed point is a pseudo cellconnected to a movable cell. By introducing fixed points, theplacement can be maintained in a force equilibrium state andfurther transformed into another equilibrium state. By relaxingsome of the previously introduced fixed points, we can partially orcompletely collapse the current placement in order to repositionthe cells, or incrementally perturb the existing good solution tofulfill additional requirements. We apply the FAR-based approach toglobal placement for total wire length minimization, and toincremental placement for Buffer Site Generation (BSG). For globalplacement, our experimental results show that the FAR methodachieves 54.4% CPU speedup and total wire length comparable to thatachieved by the constant force based approach [1]. Experimentalresults indicate that to accommodate buffers in specific regions,FAR is able to perturb incrementally a given solution in awell-controlled way.