UST/DME: a clock tree router for general skew constraints

In this article, we propose new approaches for solving the useful-skew tree (UST) routing problem [Xi and Dai 1997]: clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for the zero-skew tree (ZST) [Edahiro 1992; Chao et al. 1992] and bounded-skew tree (BST) [Cong and Koh 1995; Huang et al. 1995; Kahng and Tsao 1997; Cong et al. 1998] routings; hence, the names UST/DME and Greedy-UST/DME for our UST algorithms. Our novel contribution is that we simultaneously perform skew scheduling and tree routing so that each local skew range is incrementally refined to a skew value that minimizes the wirelength increase during the bottom-up merging phase of DME. As a result, not only is the skew schedule feasible, but also the wirelength increase is minimized at each merging step of clock tree construction. The experimental results show very encouraging improvement over the previous BST/DME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total routing wirelength.

Effective scheduling of limited communication resources is one of the critical methods for data transmission in the Internet of things. However, the time slot utilization rate of many existing resource scheduling methods of Internet of things is not high. This article proposes a new efficient resource scheduling based on routing tree and detection matrix for Internet of things. In heterogeneous Internet of things, according to the different working modes and functions, the nodes are divided into Internet of things devices, routing nodes, and base station. We use time slot multiplexing to improve the time slot utilization of continuous transmission in Internet of things. First, the time slot allocation table in a round is obtained by the time slot scheduling based on the routing tree. Then, the collision matrix and the transmission matrix are established based on the time slot allocation table in a round. Finally, the minimum time slot scheduling in continuous rounds is determined based on the routing tree and the detection matrix. The experimental results show that the resource scheduling based on routing tree and detection matrix effectively improves the utilization of time slots and improves the throughput of the Internet of things.

The problem of scheduling and tree routing in WiMAX/802.16 based mesh networks were not defined in the standard and are thus subject to extensive research. In this paper, we consider the problem of joint routing and scheduling in 802.16-based wireless mesh network, with the objective of determining a minimum length schedule that satisfies a given (uplink/downlink) end-to-end traffic demand. Minimizing the schedule length amounts to maximizing the spectrum spatial reuse by concurrently transmitting on as many links as possible, which we refer to as a transmission configuration (a group of links that can simultaneously transmit without violating the signal-to-interferenceplus- noise ratio (SINR) requirement). Our model is referred to as maximum spatial reuse (MSR). Since there is an overwhelming number of possible transmission configurations to be assigned to time slots, we adopt the column generation technique to construct our MSR model. We present two formulations for modeling MSR, namely the link-based column generation (CGLink) formulation and the path-based column generation (CGPath) formulation. These two formulations differ mainly in the number of routing decision variables. Our experimental results indicate that the path-based formulation needs much less computational (CPU) time than the link-based formulation in order to determine the (same) optimized solution with the same spatial reuse gain.

In the paper, we provide a timing-driven rectilinear routing tree algorithm which applies top-down partitioning followed by the bottom-up routing tree construction in the presence of the obstacles. The objective is to simultaneously minimize the source-to-terminal delay and the total wirelength. First, a top-down partitioning method is used to divide the chip into four sub-regions according to the position of the source. Then, the terminals in each sub-region are connected by a fast sequential routing tree algorithm. The major steps of the routing algorithm include minimal spanning tree constructing, invalid edges pushing and routing. It shows experimentally that the maximum source-to-terminal delay of the routing tree is improved by 74%. Compared to previous results, total wirelength is significantly reduced by 34.7%.

Network lifetime maximization for time-sensitive data gathering in wireless sensor networks

The problem of scheduling and routing tree construction in WiMAX/802.16 based mesh networks is not defined in the standard and has thus been the subject to extensive research. We consider the problem of joint routing and scheduling in WiMAX-based mesh networks, with the objective of determining a minimum schedule period that satisfies a given (uplink/downlink) traffic demand. Minimizing the length of a schedule amounts to maximizing the spectrum spatial reuse by activating concurrently as many links. This group of transmission links active concurrently is referred to as the transmission group and refers to the set of wireless links that can simultaneously transmit without violating the signal-to-interference-plus-noise ratio (SINR) requirement. Our model is referred to as maximum spatial reuse (MSR). We assume centralized scheduling at the base station and attempt to maximize the system throughput through appropriate routing tree selection and achieving efficient spectrum reuse through opportunistic link scheduling. We present an ILP optimization model for the joint problem, which relies on the enumeration of all possible link schedules. Given its complexity, we decompose the problem using a column generation (CG) approach. We present two formulations for modeling MSR, namely the link-based (CGLink) and the path-based (CGPath) formulation. These two formulations differ mainly in the number of routing decision variables. Our experimental results indicate that the path-based formulation needs much less computational (CPU) time than the link-based in order to determine the (same) optimal solution with the same spatial reuse gain.

The deferred-merge embedding (DME) algorithm is presented. In linear time, it embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Experimental results show that the algorithm yields exact zero skew trees with 9% to 16% wirelength reduction over previous constructions. The DME algorithm may be applied to either the Elmore or the linear delay model and yields optimal total wirelength for linear delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

PSO-based sink placement and load-balanced anycast routing in multi-sink WSNs considering compressive sensing theory

SummaryThis paper addresses the problems of relay selection, clustering, and routing to extend the lifetime of wireless body area networks. We first propose an efficient algorithm called “Energy‐aware Relay Selection and Cluster‐based Routing (ERSCR)” to develop a hybrid data aggregation tree in the network. ERSCR has three phases, including the relay selection, clustering and Cluster Head (CH) selection, and data transmission. It divides the biosensors into several clusters and selects an appropriate CH for each cluster. Each biosensor transmits data to its CH or relay node. The aggregated data are then routed to the sink through an energy‐balanced routing tree. The proposed scheme considers both residual energy and distance for routing data of biosensors. It not only reduces the energy consumption in the network but also balances the energy consumed by different biosensors. Subsequently, we improve the ERSCR algorithm and introduce the “Joint Relay Selection, Clustering, and Routing (JRSCR)” algorithm to achieve a better network performance. JRSCR benefits from the advantages of the ERSCR algorithm. Moreover, it reduces the number of transmissions with the direct use of the relay nodes as CH. As another advantage, both ERSCR and JRSCR algorithms are compatible with the natural physical states of the human body. Simulation results demonstrate the efficiency of the proposed algorithms in terms of energy consumption, network lifetime, and maximum hop count.

This paper presents a new approach for solving the Lower and Upper Bounded delay routing Tree (LUBT) problem using linear programming. LUBT is a Steiner tree rooted at the source node such that delays from the source to sink nodes lie between the given lower and upper bounds. We show that our proposed method produces minimum cost LUBT for a given topology under a linear delay model. Unlike recent works which control only the difference between the maximum and the minimum source-sink delay, we construct routing trees which satisfy distinct lower and upper bound constraints on the source-sink delays. This formulation exploits all the flexibility that is present in low power and high performance clock routing tree design.

Buffer insertion and wire sizing are critical in deep submicron VLSI design. This paper studies the problem of constructing routing trees with simultaneous buffer insertion and wire sizing in the presence of routing and buffer obstacles. No previous algorithms consider all these factors simultaneously. Previous dynamic programming based algorithm is first extended to solve the problem. However, with the size of routing graph increasing and with wire sizing taken into account, the time and space requirement increases enormously. Then a new approach is proposed to formulate the problem as a series of graph problems. The routing tree solution is obtained by finding shortest paths in a series of graphs. In the new approach, wire sizing can be handled almost without any additional time and space requirement, Moreover, the time and space requirement is only polynomial in terms of the size of routing graph. Our algorithm differs from traditional dynamic programming, and is capable of addressing the problem of inverter insertion and sink polarity. Both theoretical and experimental results show that the graph-based algorithm outperforms the DP-based algorithm by a large margin. We also propose a hierarchical approach to construct routing tree for a large number of sinks.

In Deep sub-micron design level, interconnect plays an important role in VLSI circuit designs. Traditional interconnects are facing several challenges such as delay and power dissipation. Graphene nanoribbons (GNRs) have been found to be potential alternative for both transistors and interconnects due to its outstanding electrical and thermal properties. The construction of minimum cost global routing trees is a key challenge in deep sub-micron design. The construction of such trees for traditional interconnects based on Required Arrival Time (RAT) has been reported in literature. The construction of global routing trees for GNR routing are different than that of traditional interconnects. In this paper, we propose an algorithm for the construction of cost effective global routing trees for GNR routing based on required arrival time. We formulate the GNR routing problem considering the minimization of the area of triangular grid such that delay from source to each of the sink terminals is within the given time budget. The algorithm is tested on a random set of data and the results obtained are quite encouraging.

As devices and lines shrink into the deep submicron range, the propagation delay of signals can be effectively improved by repowering the signals using intermediate buffers placed within the routing trees. Almost no existing timing driven floorplanning and placement approaches consider the option of buffer insertion. As such, they may exclude solutions, particularly early in the design process, with smaller overall area and better routability. In this paper, we propose a new methodology in which buffered trees are used to estimate wire delay during floorplanning. Instead of treating delay as one of the objectives, as done by the majority of previous work, we formulate the problem in terms of delay bounded buffered trees (DBB-tree) and propose an efficient algorithm to construct a DBB spanning tree for use during floorplanning. Experimental results show that the algorithm is very effective. Using buffer insertion at the floorplanning stage yields significantly better solutions in terms of both chip area and total wire length.

A 3.4713-approximation algorithm for the capacitated multicast tree routing problem

Longest‐path routing problems, which can arise in the design of high‐performance printed circuit boards (PCBs), have been proven to be NP‐hard. In this article, we propose a constraint programming (CP) formulation and a mixed integer linear programming (MILP) formulation to gridded longest‐path routing problems; each of which may contain obstacles. After a longest‐path routing problem has been transformed into a CP problem, a CP solver can be used to find optimal solutions. On the other hand, parallel MILP solvers can be used to find optimal solutions after the longest‐path routing problem has been transformed into an MILP problem. Also, suboptimal solutions can be generated in exchange for reduced execution time. The proposed formulation methods can also be used to solve shortest‐path routing problems. Experimental results show that more than 3,700x speed‐up can be achieved by using a parallel MILP solver with 16 threads in solving formulated longest‐path routing problems. The execution time can be further reduced if a computer containing more processer cores is available.