UST/DME

In this paper, we propose new approaches for solving the useful-skew tree (UST) routing problem [17]: Clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for zero-skew tree [5; 1] and bounded-skew tree [8; 2] routings; hence, the names UST/DME and Greedy-UST/DME for our algorithms. They simultaneously perform skew scheduling and tree routing such that each local skew range is incrementally refined to a skew value that minimizes the wirelength during the bottom-up merging phase of DME. The resulting skew schedule is not only feasible, but is also best for routing in terms of wirelength. The experimental results show very encouraging improvement over the previous BST/DME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total wirelength.

The problem of scheduling and tree routing in WiMAX/802.16 based mesh networks were not defined in the standard and are thus subject to extensive research. In this paper, we consider the problem of joint routing and scheduling in 802.16-based wireless mesh network, with the objective of determining a minimum length schedule that satisfies a given (uplink/downlink) end-to-end traffic demand. Minimizing the schedule length amounts to maximizing the spectrum spatial reuse by concurrently transmitting on as many links as possible, which we refer to as a transmission configuration (a group of links that can simultaneously transmit without violating the signal-to-interferenceplus- noise ratio (SINR) requirement). Our model is referred to as maximum spatial reuse (MSR). Since there is an overwhelming number of possible transmission configurations to be assigned to time slots, we adopt the column generation technique to construct our MSR model. We present two formulations for modeling MSR, namely the link-based column generation (CGLink) formulation and the path-based column generation (CGPath) formulation. These two formulations differ mainly in the number of routing decision variables. Our experimental results indicate that the path-based formulation needs much less computational (CPU) time than the link-based formulation in order to determine the (same) optimized solution with the same spatial reuse gain.

PSO-based sink placement and load-balanced anycast routing in multi-sink WSNs considering compressive sensing theory

SummaryThis paper addresses the problems of relay selection, clustering, and routing to extend the lifetime of wireless body area networks. We first propose an efficient algorithm called “Energy‐aware Relay Selection and Cluster‐based Routing (ERSCR)” to develop a hybrid data aggregation tree in the network. ERSCR has three phases, including the relay selection, clustering and Cluster Head (CH) selection, and data transmission. It divides the biosensors into several clusters and selects an appropriate CH for each cluster. Each biosensor transmits data to its CH or relay node. The aggregated data are then routed to the sink through an energy‐balanced routing tree. The proposed scheme considers both residual energy and distance for routing data of biosensors. It not only reduces the energy consumption in the network but also balances the energy consumed by different biosensors. Subsequently, we improve the ERSCR algorithm and introduce the “Joint Relay Selection, Clustering, and Routing (JRSCR)” algorithm to achieve a better network performance. JRSCR benefits from the advantages of the ERSCR algorithm. Moreover, it reduces the number of transmissions with the direct use of the relay nodes as CH. As another advantage, both ERSCR and JRSCR algorithms are compatible with the natural physical states of the human body. Simulation results demonstrate the efficiency of the proposed algorithms in terms of energy consumption, network lifetime, and maximum hop count.

The problem of scheduling and routing tree construction in WiMAX/802.16 based mesh networks is not defined in the standard and has thus been the subject to extensive research. We consider the problem of joint routing and scheduling in WiMAX-based mesh networks, with the objective of determining a minimum schedule period that satisfies a given (uplink/downlink) traffic demand. Minimizing the length of a schedule amounts to maximizing the spectrum spatial reuse by activating concurrently as many links. This group of transmission links active concurrently is referred to as the transmission group and refers to the set of wireless links that can simultaneously transmit without violating the signal-to-interference-plus-noise ratio (SINR) requirement. Our model is referred to as maximum spatial reuse (MSR). We assume centralized scheduling at the base station and attempt to maximize the system throughput through appropriate routing tree selection and achieving efficient spectrum reuse through opportunistic link scheduling. We present an ILP optimization model for the joint problem, which relies on the enumeration of all possible link schedules. Given its complexity, we decompose the problem using a column generation (CG) approach. We present two formulations for modeling MSR, namely the link-based (CGLink) and the path-based (CGPath) formulation. These two formulations differ mainly in the number of routing decision variables. Our experimental results indicate that the path-based formulation needs much less computational (CPU) time than the link-based in order to determine the (same) optimal solution with the same spatial reuse gain.

This paper presents a new approach for solving the Lower and Upper Bounded delay routing Tree (LUBT) problem using linear programming. LUBT is a Steiner tree rooted at the source node such that delays from the source to sink nodes lie between the given lower and upper bounds. We show that our proposed method produces minimum cost LUBT for a given topology under a linear delay model. Unlike recent works which control only the difference between the maximum and the minimum source-sink delay, we construct routing trees which satisfy distinct lower and upper bound constraints on the source-sink delays. This formulation exploits all the flexibility that is present in low power and high performance clock routing tree design.

In Deep sub-micron design level, interconnect plays an important role in VLSI circuit designs. Traditional interconnects are facing several challenges such as delay and power dissipation. Graphene nanoribbons (GNRs) have been found to be potential alternative for both transistors and interconnects due to its outstanding electrical and thermal properties. The construction of minimum cost global routing trees is a key challenge in deep sub-micron design. The construction of such trees for traditional interconnects based on Required Arrival Time (RAT) has been reported in literature. The construction of global routing trees for GNR routing are different than that of traditional interconnects. In this paper, we propose an algorithm for the construction of cost effective global routing trees for GNR routing based on required arrival time. We formulate the GNR routing problem considering the minimization of the area of triangular grid such that delay from source to each of the sink terminals is within the given time budget. The algorithm is tested on a random set of data and the results obtained are quite encouraging.

The deferred-merge embedding (DME) algorithm is presented. In linear time, it embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Experimental results show that the algorithm yields exact zero skew trees with 9% to 16% wirelength reduction over previous constructions. The DME algorithm may be applied to either the Elmore or the linear delay model and yields optimal total wirelength for linear delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 3.4713-approximation algorithm for the capacitated multicast tree routing problem

Intellectual properties (IPs) in design form are integrated for incremental design of system-on-chip (SoC). In order to realize proper functionality of an SoC, some global signal nets are often needed to be connected between the design IPs. If the component IPs are in-house, the global nets may be routed through the routing region of the design IPs and this routing may be formulated as an adaptive incremental routing problem where all the routing issues need to be tackled directly in the detailed routing phase only. In this work, we propose a technique for adaptive incremental routing of global nets with the objectives of minimal increase in wire length, congestion, and number of vias. The first objective maintains the desired frequency, the second and the third ones reduce the power overhead, and specifically the third one is effective in keeping the layout manufacture-friendly. The proposed technique is applied on some ISCAS’85 benchmarks and finally on a crypto SoC design which integrates several component designs for crypto-cores. The results on CPU time for routing and the overhead of routing are encouraging.

Chip-level clock tree synthesis (CCTS) is a key problem that arises in complex system-on-a-chip designs. A key requirement of CCTS is to balance the clock-trees belonging to different IPs such that the entire tree has a small skew across all process corners. Achieving this is difficult because the clock trees in different IPs might be vastly different in terms of their clock structures and cell/interconnect delays. The chip-level clock tree is expected to compensate for these differences and achieve good skews across all corners. Also, CCTS is expected to reduce clock divergence between IPs that have critical timing paths between them. Reducing clock divergence reduces the maximum possible clock skew in the critical paths between the IPs and thus improves yield. This paper proposes effective CCTS algorithms to simultaneously reduce multicorner skew and clock divergence. Experimental results on several test-cases indicate that our methods achieve 30% reduction in the clock divergence with significantly improved multicorner skew variance, at the cost of 2% increase in buffer area and 1% increase in wirelength.

In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role on determining circuit quality indicated by timing, power consumption, cost, power supply noise and tolerance to process variations. In this paper, a clock tree routing algorithm is proposed to achieve any prescribed non-zero skews which are useful in reducing clock cycle time, suppressing power supply noise and improving tolerance to process variations. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area which imply cost, power consumption and vulnerability to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper skew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the proposed algorithm can reduce the total wire and buffer capacitance by 60% over an extension of existing zero skew routing method.

Two-tier particle swarm optimization protocol for clustering and routing in wireless sensor network

Clock trees can be constructed based on static arrival time constraints or dynamic implied skew constraints. Dynamic implied skew constraints allow the full timing margins to be utilized. However, the dynamic skew constraints require a high run-time complexity to be evaluated. In contrast, static arrival time constraints are more restrictive but can be evaluated in constant time. Consequently, there is a tradeoff between timing margin utilization and run-time. In this paper, a scalable clock tree synthesis (CTS) framework is proposed for the construction of low-cost useful skew trees (USTs) with high timing quality. The scalability is based on combining the use of arrival time constraints with virtual minimum and maximum delay offsets, which facilitates that a pair of smaller subtrees can be joined into a larger subtree in constant time. The ability to quickly join subtrees is leveraged to perform a high degree of solution space exploration, which translates into the construction of USTs with low-cost. In particular, clock trees with various routing tree topologies, buffer tree topologies, buffer sizes, and stem wire lengths are explored. Moreover, the arrival time constraints are specified with the objective of being the least restrictive to reduce cost. Furthermore, the constraints are respecified throughout the tree construction process using a slack graph (SG) to expose additional timing margins. The high timing quality is obtained by seamlessly integrating arbitrary timing models using the SG. Finally, the proposed CTS framework is integrated with a clock tree optimization framework to demonstrate that the constructed USTs are capable of meeting timing constraints under the influence of on-chip variations.

A model to facilitate a better routing of a multiterminal net under obstacle constraints is presented. The model is applied to the clock tree routing problem. Using this model, in conjunction with simple routines, all possible locations of a Steiner node in the routing plane are determined. As a result, less wire length is achieved compared to other methods. The model has been incorporated in a local modification algorithm to efficiently implement engineering change orders (ECOs) of clock trees.