Buffered clock tree for high quality IC design

Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional works that handle this problem with clock routing or buffer sizing, this paper proposes a novel register clustering algorithm in generating the leaf level topology of the clock tree to reduce the power consumption. Aiming to guarantee the stability of our register clustering algorithm, an effective initialization algorithm called “K-Splitting” and a “Pseudo Center” technology are developed. Meanwhile, a buffer allocation algorithm is proposed to satisfy the slew constraints within the clusters at a minimum cost of power consumption. We implement the clock tree synthesis (CTS) flow in [2] to test our approach on ISPD'10 benchmark circuits. Experimental results show that our register clustering algorithm achieves a 29.0% reduction in power consumption as well as a 5.7% reduction in max latency without affecting the clock skew. Moreover, the total runtime of the CTS flow with our register clustering algorithm is significantly reduced by 87.3%.

Chip-level clock tree synthesis (CCTS) is a key problem that arises in complex system-on-a-chip designs. A key requirement of CCTS is to balance the clock-trees belonging to different IPs such that the entire tree has a small skew across all process corners. Achieving this is difficult because the clock trees in different IPs might be vastly different in terms of their clock structures and cell/interconnect delays. The chip-level clock tree is expected to compensate for these differences and achieve good skews across all corners. Also, CCTS is expected to reduce clock divergence between IPs that have critical timing paths between them. Reducing clock divergence reduces the maximum possible clock skew in the critical paths between the IPs and thus improves yield. This paper proposes effective CCTS algorithms to simultaneously reduce multicorner skew and clock divergence. Experimental results on several test-cases indicate that our methods achieve 30% reduction in the clock divergence with significantly improved multicorner skew variance, at the cost of 2% increase in buffer area and 1% increase in wirelength.

Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult. Based on that observation, in this paper, we present a novel clock tree design style, called type-matching clock tree, to ensure that the logic gates at the same level are in the same type. We prove that any clock control logic can always be transformed to our type-matching clock tree. Then, based on the idea of type-matching clock tree, we propose a zero skew gated clock tree synthesis algorithm. Compared with the industry- strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.

The German Artificial Sphincter System (GASS) project aims at the development of an implantable sphincter prosthesis driven by a micropump. During the last few years the feasibility of the concept has been proven. At present our team’s effort is focused on the compliance to safety regulations and on a very low power consumption of the system as a whole. Therefore a low-voltage multilayer piezoactuator has been developed to reduce the driving voltage of the micropump from approximately 300 Vpp to 40 Vpp. Doing so, the driving voltage is within the limits set by the regulations for active implants. The operation of the micropump at lower voltages, achieved using multilayer piezoactuators, has already resulted in a much better power efficiency. Nevertheless, in order to further reduce power consumption, we have also developed an innovative driving technique that we are going to describe and compare to other driving systems. A direct switching circuit has been developed where the buffer capacitor of the step-up converter has been replaced by the equivalent capacitance of the actuator itself. This avoids the switching of the buffer capacitor to the actuator, which would result in a very low efficiency. Usually, a piezoactuator needs a bipolar voltage drive to achieve maximum displacement. In our concept, the voltage inversion across the actuator is done using an h-bridge circuit, allowing the employment of one step-up converter only. The charge stored in the actuator is then partially recovered by means of a step-down converter which stores back the energy at the battery voltage level. The power consumption measurements of our concept are compared to a conventional driving output stage and also with inductive charge recovery circuits. In particular, the main advantage, compared to the latter systems, consists in the small inductors needed for the power converter. Other charge recovery techniques require very big inductors in order to have a significant power reduction with the capacitive loads we use in our application. With our design we will be able to achieve approximately 55% reduction in power consumption compared to the simplest conventional driver and 15% reduction compared to a charge recovery driver.

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal which incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point which renders the conventional design flow of placement followed by clock tree synthesis ineffective to obtain a high quality clock tree with low clock skew. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by clock tree synthesis and clock splitter insertion, and then performs a second stage of global placement to re-place both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is re-synthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. In addition, the total wirelength of data signals and clock signal is optimized concurrently. After legalizing the placement of all cells, our placement refinement method can be run to further reduce the clock skew. Compared with the previous state-of-the-art work, on average we can reduce the total half-perimeter wirelength and clock skew by 9% and 31%. respectively.

Pseudo functional K Longest Path Per Gate (KLPG) test (PKLPG) is proposed to generate delay tests that test the longest paths while having power supply noise similar to that seen during normal functional operation. Our experimental results show that PKLPG is more vulnerable to under-testing than traditional two-cycle transition fault test. In this work, a simulation-based X'Filling method, Bit-Flip, is proposed to maximize the power supply noise during PKLPG test. Given a set of partially-specified scan patterns, random filling is done and then an iterative procedure is invoked to flip some of the filled bits, to increase the effective weighted switching activity (WSA). Experimental results on both compacted and uncompacted test patterns are presented. The results demonstrate that our method can significantly increase effective WSA while limiting the fill rate.

Simultaneous switching events in the clock lines and almost simultaneous switching events of sequential and combinational logic elements cause large L/spl middot/di/dt and IR voltage variations in the power and ground network of a circuit. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose a genetic algorithm based clock scheduling approach for minimizing the number of simultaneous switching events such that the power supply noise is suppressed. We ensure that in any generation of the genetic algorithm process, there will be feasible clock schedules present in the gene pool by the use of gene therapy. Experimental results on benchmark circuits show an average reduction of 26.2% in the peak current, an average reduction of 37.9% in the current swing, and an average reduction of 46.2% in voltage variations in the power lines.

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

Clock gating is recognized as one of the most effective techniques to reduce the dynamic power consumption. Many research efforts have been paid to build activity-driven clock trees for low power designs. On the other hand, as the feature size continues to shrink, the on-chip-variation (OCV) effect has become a serious concern, especially for the clock skew of the top-level clock tree. Based on this observation, in this paper, we present the first work for the synthesis of OCV-aware top-level activity-driven clock trees. In our approach, the clock skew variation is considered during the top-level activity-driven clock tree synthesis. Our objective is to minimize the weighted sum of the worst timing slack and the power consumption. Compared with previous works, benchmark data consistently show that our approach can greatly increase the worst timing slack with a small overhead on the power consumption.

Presently design of a linear and wide range voltage controlled oscillator for analog and mixed mode signal applications with lesser design cycle time is a challenging work for Electronics Engineers. Band Gap reference voltage source is required, since the power supply noise is one of the important factors that affect the PLL noise performance. This paper describes the new design technique of the Band Gap Reference Current Starved Voltage Controlled Oscillator (BG-CSVCO) circuit to reduce power supply noise for PLL application. The BG-CSVCO circuit is designed and simulated using 0.18μm CMOS Technology. The BG-CSVCO has frequency range from 1.59 MHz to 2.87 GHz for the tuning range 0.2V to 1.8V and power consumption is 1.336mW. The supply voltage VDD is 1.8V.

The scaling of circuit design technology to ultra deep submicron has increased the sensitivity of circuit technology to various noise mechanisms such as power supply noise and leakage current noise, etc. The propagation of noise can happen through various modes like the power supply and the substrate to a sensitive receptor. The power supply noise can reduce the actual voltage level reaching a device, results in the loss of signal integrity. The type of noise may also cause the degradation of switching speed, timing faults, or logic functional failures. In this paper, a new approach is presented for the test generation of power supply noise in digital circuits, the approach is based on the binary decision diagrams. The test vectors of power supply noise are generated by building and operating several binary decision diagrams, such as the binary decision diagrams respectively corresponding to the normal circuits and the circuits whose signal lines have been assigned special logic values. A lot of experimental results show that if there are test vectors for the power supply noise in a circuit, then the test vectors can be generated by the approach proposed in this paper.

In this paper, a new clock tree distribution design flow and algorithm of clock gates splitting to improve the clock tree power dissipation had been presented. The clock gating components are inserted in clock tree during VLSI design flow to reduce clock tree dynamic power consumption. The effective splitting and physical placement of the clock gates are vital to ensure the clock gating efficiency. The paper presents an approach that is able to achieve optimum power saving on clock tree during full operation mode and shut off mode.

In deep sub-micron technologies post-layout tuning analysis has become the most critical phase in the verification of large system-on-chip (SoC) designs with several power-hungry blocks. An increasingly important factor that can introduce a severe performance loss is the power supply noise. As technology advances into the nanometer regime, the operating frequencies increase, and clock gating has emerged as an effective technique to limit the power consumption in block-based designs. As a consequence, the amplitude of the supply voltage fluctuations has reached values where techniques to include the effect of power supply noise into timing analysis based on linear models are no longer adequate, and the non-linear dependence of cell delay from supply voltage must be considered. In this work we present a practical methodology that accurately takes into account the power supply noise effects in static timing analysis, which can be seamlessly included into an industrial sign-off design flow. The experimental results obtained from the timing verification of an industrial SoC design have demonstrated the effectiveness of our approach

Boundary optimization of buffered clock trees for low power

Large scale synchronous network-on-chip (NoC) requires complex clock tree design, which leads to a large area overhead and power consumption. Based on handshaking protocols, asynchronous NoC does not have global clock tree distribution, which results in a natural power saving mode without any explicit clock gating. However, the faults occurring in such asynchronous networks will seriously affect their performances. In this paper, we propose AFTER, an Asynchronous Fault-TolErant Router, which uses the quasi delay insensitive (QDI) logic. The proposed router is able to detect the faults of ports and links. Then, a fault-tolerant routing mechanism, based on the port priority in different quadrants, is proposed to maximize the number of packets that can be transmitted via the shortest paths. In this way, the fault-tolerance of asynchronous routers can be achieved. Besides that, AFTER could also achieve high scalability, and is suitable for the large scale globally asynchronous locally synchronous (GALS) system. The experimental results show that, when faults occur in the network, AFTER has a better fault-tolerance performance than the reference.