A technique to construct global routing trees for graphene nanoribbon (GNR)

In deep sub-micron regime, interconnect delays dominate VLSI circuit design. Thus, construction of cost-effective global routing trees is key to such designs. In order to reduce the interconnect delay, traditional Manhattan (M-) routing architectures are currently being replaced by the diagonal X architectures. A recent routing architecture is based on Y interconnects, involving the pervasive use of 0/spl deg/, 60/spl deg/, and 120/spl deg/ oriented global and semi-global wirings. Unlike the X-routing, Y-routing Is observed to support regular routing grid, which as important for simplifying manufacturing processes and routing and design rule checking algorithms. In this paper, we propose a novel Y-routing algorithm which can solve reasonably sized problems in nominal time. The proposed method is capable of finding routing solutions for problem instances which could not be solved in reasonable time by some recently reported methods. Moreover, it can be easily extended for routing with any uniform orientation.

In the paper, we provide a timing-driven rectilinear routing tree algorithm which applies top-down partitioning followed by the bottom-up routing tree construction in the presence of the obstacles. The objective is to simultaneously minimize the source-to-terminal delay and the total wirelength. First, a top-down partitioning method is used to divide the chip into four sub-regions according to the position of the source. Then, the terminals in each sub-region are connected by a fast sequential routing tree algorithm. The major steps of the routing algorithm include minimal spanning tree constructing, invalid edges pushing and routing. It shows experimentally that the maximum source-to-terminal delay of the routing tree is improved by 74%. Compared to previous results, total wirelength is significantly reduced by 34.7%.

Graphene nanoribbon based interconnect has several advantageous properties over traditional interconnect like power dissipation, delay, and integration capability. But each wire segment of Graphene nanoribbon based interconnect has a chance of failure as each wire segment is associated with some survival probability. Hence reliability issues can play a major role in the routing of this type of interconnect. In this paper, we propose an algorithm for global routing of Graphene nanoribbon based interconnect considering reliability as an optimization function with minimum increase in cost. The cost due to routing of Graphene nanoribbon based interconnect depends on the interconnect length, angle of bending, and the number of bending, and this is known as the hybrid cost. The experiment is done on a random data set and the result shows the effectiveness of the method. KeywordsGraphene nanoribbonSurvival probabilityRouting reliabilityHybrid cost

The problem of scheduling and routing tree construction in WiMAX/802.16 based mesh networks is not defined in the standard and has thus been the subject to extensive research. We consider the problem of joint routing and scheduling in WiMAX-based mesh networks, with the objective of determining a minimum schedule period that satisfies a given (uplink/downlink) traffic demand. Minimizing the length of a schedule amounts to maximizing the spectrum spatial reuse by activating concurrently as many links. This group of transmission links active concurrently is referred to as the transmission group and refers to the set of wireless links that can simultaneously transmit without violating the signal-to-interference-plus-noise ratio (SINR) requirement. Our model is referred to as maximum spatial reuse (MSR). We assume centralized scheduling at the base station and attempt to maximize the system throughput through appropriate routing tree selection and achieving efficient spectrum reuse through opportunistic link scheduling. We present an ILP optimization model for the joint problem, which relies on the enumeration of all possible link schedules. Given its complexity, we decompose the problem using a column generation (CG) approach. We present two formulations for modeling MSR, namely the link-based (CGLink) and the path-based (CGPath) formulation. These two formulations differ mainly in the number of routing decision variables. Our experimental results indicate that the path-based formulation needs much less computational (CPU) time than the link-based in order to determine the (same) optimal solution with the same spatial reuse gain.

In wireless sensor network, many sensor nodes are distributed in the field. They communicate the sensing data each other and forward it to sink. Routing protocols, which define the delivery methods of sending data, affect to the lifetime of sensor network. This paper proposes RTAF that is a routing-tree construction algorithm of sensor nodes by a single flooding process in wireless sensor network. A routing tree is constructed by selecting a parent node using the forward-direction flooding packet and gathering children nodes using the reverse-direction flooding packet. In this process, a node with much energy becomes the parent node. And the routing tree is periodically reconstructed in order to distribute the loads of parent nodes. The proposed algorithm compared performance with Modified-LEACH using NS2 network simulation tool. The simulation result shows that the proposed algorithm constructs a routing-tree faster and reduced 40-80% in routing-tree construction packet.

Coupling Of Synthesis And Layout: Challenges And Solutions

Previous literature on VLSI routing and wiring estimation typically assumes a one-to-one correspondence between terminals and ports. In practice, however (say, in a gridded routing regime), each \terminal consists of a large collection of electrically equivalent ports, a fact that is not accounted for in layout steps such as wiring estimation. The presence of multiple ports for a given terminal gives rise to the group Steiner minimal tree problem. In this paper, we address the general problem of minimum-cost routing tree construction in the presence of multi-port terminals. Our main result is the rst known heuristic with a sub-linear performance bound. In particular, for a net with k multi-port terminals, previous heuristics have a performance bound of (k 1) OPT , while our construction o ers an improved performance bound of (1 + ln k 2 ) pk OPT . Our Java implementation is available on the World Wide Web.

The literature on programming sensor networks has focused so far on providing higher-level abstractions for expressing local node behavior. Kairos is a natural next step in sensor network programming in that it allows the programmer to express, in a centralized fashion, the desired global behavior of a distributed computation on the entire sensor network. Kairos’ compile-time and runtime subsystems expose a small set of programming primitives, while hiding from the programmer the details of distributed-code generation and instantiation, remote data access and management, and inter-node program flow coordination. In this paper, we describe Kairos’ programming model, and demonstrate its suitability, through actual implementation, for a variety of distributed programs—both infrastructure services and signal processing tasks—typically encountered in sensor network literature: routing tree construction, localization, and object tracking. Our experimental results suggest that Kairos does not adversely affect the performance or accuracy of distributed programs, while our implementation experiences suggest that it greatly raises the level of abstraction presented to the programmer.

Graphene, the one-atom-thick two-dimensional (2D) carbon material, has attracted tremendous interest in both academia and industry due to its outstanding electrical, mechanical, and thermal properties. For electronic applications, the challenging task is to make it as a semiconductor. The bottom-up synthesis of semiconducting one-dimensional (1D) nanometer-wide graphene strips, namely, graphene nanoribbons (GNRs), has attracted much attention owing to its promising electronic, optical, and magnetic properties. In this regard, we report the fabrication of cove-type 2D GNR networks (GNNs) via the interconnection of 1D self-assembled GNRs on the surface of Au(111). The cove-type 2D GNRs networks (GNNs) were fabricated from the GNR, 5-CGNR-1-1, synthesized using the precursor of DBSP. Annealing of high-density self-assembled GNRs on the surface of Au(111) through two-zone chemical vapour deposition (2Z CVD) successfully generated a 2D interconnected structure with high yield via the fusion and ladder coupling reactions of GNR chains. In order to validate the later fusion reaction, we have also synthesized the GNR, 7-AGNR-1-1, using the precursor of DBBA. The GNNs, which consist of hybridized metallic-like and semiconducting GNRs, are a new class of carbon-based materials. Further, we applied this material for thermoelectric (TE) applications and found a very low cross-plane thermal conductivity of 0.11 Wm-1 K-1 , which is one of the lowest value among the carbon-based materials as well as inorganic semiconductors, while maintaining the cross-plane electrical conductivity of 188 S m-1 .

Computational study on the order-of-magnitude difference in thermal conductivity between graphene and graphane nanoribbons

Topological analysis is used in several domains to identify and characterize important features in scientific data, and is now one of the established classes of techniques of proven practical use in scientific computing. The growth in parallelism and problem size tackled by modern simulations poses a particular challenge for these approaches. Fundamentally, the global encoding of topological features necessitates interprocess communication that limits their scaling. In this paper, we extend a new topological paradigm to the case of distributed computing, where the construction of a global merge tree is replaced by a distributed data structure, the merge forest, trading slower individual queries on the structure for faster end-to-end performance and scaling. Empirically, the queries that are most negatively affected also tend to have limited practical use. Our experimental results demonstrate the scalability of both the merge forest construction and the parallel queries needed in scientific workflows, and contrast this scalability with the two established alternatives that construct variations of a global tree.

Buffer insertion and wire sizing are critical in deep submicron VLSI design. This paper studies the problem of constructing routing trees with simultaneous buffer insertion and wire sizing in the presence of routing and buffer obstacles. No previous algorithms consider all these factors simultaneously. Previous dynamic programming based algorithm is first extended to solve the problem. However, with the size of routing graph increasing and with wire sizing taken into account, the time and space requirement increases enormously. Then a new approach is proposed to formulate the problem as a series of graph problems. The routing tree solution is obtained by finding shortest paths in a series of graphs. In the new approach, wire sizing can be handled almost without any additional time and space requirement, Moreover, the time and space requirement is only polynomial in terms of the size of routing graph. Our algorithm differs from traditional dynamic programming, and is capable of addressing the problem of inverter insertion and sink polarity. Both theoretical and experimental results show that the graph-based algorithm outperforms the DP-based algorithm by a large margin. We also propose a hierarchical approach to construct routing tree for a large number of sinks.

In this article, we propose new approaches for solving the useful-skew tree (UST) routing problem [Xi and Dai 1997]: clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for the zero-skew tree (ZST) [Edahiro 1992; Chao et al. 1992] and bounded-skew tree (BST) [Cong and Koh 1995; Huang et al. 1995; Kahng and Tsao 1997; Cong et al. 1998] routings; hence, the names UST/DME and Greedy-UST/DME for our UST algorithms. Our novel contribution is that we simultaneously perform skew scheduling and tree routing so that each local skew range is incrementally refined to a skew value that minimizes the wirelength increase during the bottom-up merging phase of DME. As a result, not only is the skew schedule feasible, but also the wirelength increase is minimized at each merging step of clock tree construction. The experimental results show very encouraging improvement over the previous BST/DME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total routing wirelength.

The thermal transport properties of the electrons in stanene nanoribbons (SNRs) and graphene nanoribbons (GNRs) are studied using a nonequilibrium Green's function approach in which the effects of electron-phonon coupling are considered. The results demonstrate that the electron thermal conductance values in both SNRs and GNRs are closely related to both the temperature T and the chemical potential μ. Comparison with the thermal transport properties of GNRs shows that the quantized thermal conductance plateau in SNRs is narrower at low temperatures, while the thermal conductance is also greater at higher temperatures in SNRs. The periodic strain-induced electron-phonon coupling can modulate the thermal conductance periodically in both SNRs and GNRs.

Graphane and graphene are both two-dimensional materials but of different bonding configurations, which can result in distinct thermal conduction properties. We simulate thermal conduction in graphane nanoribbons (GANRs) using the nonequilibrium Green's function method. We find anisotropic thermal conduction in GANRs, with zigzag GANRs giving higher thermal conductance than armchair ones. Compared to the graphene counterparts, GANRs show lower ballistic thermal conductance and stronger thermal conductance anisotropy. Furthermore, hydrogen vacancies of GANRs considerably suppress thermal conduction, accompanied by enhanced thermal conductance anisotropy. The tunable thermal conduction, realized by controlling the ribbon width, edge shape, and hydrogen vacancy concentration of GANRs, could be useful for thermal management and thermoelectric applications.