A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI

In Deep sub-micron design level, interconnect plays an important role in VLSI circuit designs. Traditional interconnects are facing several challenges such as delay and power dissipation. Graphene nanoribbons (GNRs) have been found to be potential alternative for both transistors and interconnects due to its outstanding electrical and thermal properties. The construction of minimum cost global routing trees is a key challenge in deep sub-micron design. The construction of such trees for traditional interconnects based on Required Arrival Time (RAT) has been reported in literature. The construction of global routing trees for GNR routing are different than that of traditional interconnects. In this paper, we propose an algorithm for the construction of cost effective global routing trees for GNR routing based on required arrival time. We formulate the GNR routing problem considering the minimization of the area of triangular grid such that delay from source to each of the sink terminals is within the given time budget. The algorithm is tested on a random set of data and the results obtained are quite encouraging.

Previous literature on VLSI routing and wiring estimation typically assumes a one-to-one correspondence between terminals and ports. In practice, however (say, in a gridded routing regime), each \terminal consists of a large collection of electrically equivalent ports, a fact that is not accounted for in layout steps such as wiring estimation. The presence of multiple ports for a given terminal gives rise to the group Steiner minimal tree problem. In this paper, we address the general problem of minimum-cost routing tree construction in the presence of multi-port terminals. Our main result is the rst known heuristic with a sub-linear performance bound. In particular, for a net with k multi-port terminals, previous heuristics have a performance bound of (k 1) OPT , while our construction o ers an improved performance bound of (1 + ln k 2 ) pk OPT . Our Java implementation is available on the World Wide Web.

3D floorplanning of low-power and area-efficient Network-on-Chip architecture

The authors present a design approach for an arithmetic macrocell that computes the scalar product of two vectors, an operation ubiquitously present in the solution of many communications and digital signal processing problems. The core of the proposed architecture is a full combinational design containing a partial product generator, a partial product accumulator and a vector accumulator. The design addresses the competing optimisation goals of VLSI area, power dissipation and latency in the deep submicron regime. Compared with conventional merged arithmetic architectures, the proposed macrocell design represents a substantial improvement in the VLSI layout with little area wastage, a high degree of regularity and a good scalability for different vector lengths and operand widths. A theoretical analysis shows that the design of a 16-bit scalar product multiplier for input vectors with 16 elements, in comparison with traditionally designed architecture, achieves a saving of 38.6% in the silicon area, an up to 73% increase in the area usage efficiency and a 29.4% saving in the interconnect delay. Post-layout simulations of the proposed circuit, based on a 0.18 /spl mu/m CMOS process, show an average power dissipation of 64.96 mW and a latency of 6.92 ns at a standard supply voltage of 1.8 V, a superior performance for a single cycle instruction in a high-speed, low voltage 16-bit digital signal processor operating at 144 MHz. The use of shorter interconnects and more equalised interconnect delays, leads to the power dissipation and delay incurred by the interconnects being substantially reduced. Post-layout simulation of our proposed circuit at supply voltages ranging from 0.7 to 3.3 V shows a significant power reduction of 6 to 13% over the pre-layout simulation results of the conventional design.

A general purpose processor used to consist of a single processing core, which performed and controlled all tasks on the chip. Due to the continuous increase of the number of transistors available on-chip and the operational clock frequency, it became impossible to reach every function within the chip in a single clock cycle. Furthermore, centralized control became hard with the increase in functionality. This lead to the current move towards integrating a set of independent processing cores into a single chip. These multi-core architectures rely on a well designed on-chip communication architecture. Global wires and bus-based systems need to be replaced to overcome the problem of wiring and the single point of arbitration. This is introduced as the Network-on-Chip (NoC) paradigm. In this work we explore the paradigm by implementation and characterization of multiple NoC router architectures. The scope of the communication architecture is the embedding in a heterogeneous multi-core System-on-Chip for streaming applications. Based on application analysis we propose a circuit switched router architecture and improve an existing packet switched router architecture that also oers QoS. The two routers are compared in-depth with two other packet switched router design on both latency and energy performance. Furthermore, to speed-up cycle and bit-accurate simulations, we developed a framework for large many-core architectures on a single FPGA using a sequential simulation approach.

The demands of future computing have led to challenges of very deep submicron (DSM) regime. As a result, leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as threshold voltage becomes small, according to the International Technology Roadmap for Semiconductors (ITRS). In this paper a new low leakage power technique, named “MTSCStack” has been proposed. The proposed method is based on reducing leakage power in active mode and standby mode while saving exact logic state during sleep mode. Library designed using 65 nm BSIM 4 model of Berkeley Predictive Technology Model (BPTM) has been used to simulate proposed technique.

A major challenge for the service providers in smart cities operating in domains such as health, security, maintenance, etc. is to provide efficient assignments of personnel to handle the incidents related to their services. These incidents could be divided into two categories. The first category is called scheduled events like regular maintenance operations, whose information is available in prior. The second category is called dynamic events and consists of emergency events that occur unpredictably at any time which we call dynamic events. The goal is to assign a common set of personnel efficiently to both the categories simultaneously, to reduce average service time of each event. Typically, in large scenarios, heuristics like greedy algorithms are used to obtain solutions in real time to facilitate immediate handling of dynamic events. However, they are myopic and cannot deliver optimized solutions across a large horizon. We propose a method for large scenarios in real time that are more globally optimized as compared to greedy algorithms. The proposed method involves a) A newly developed Mixed Integer Linear Program formulation, which considers multiple independent events that need to be handled parallelly, and b) Decomposition of the large scenario into a queue of smaller batches of events based on their occurrence/requested time. This method handles dynamically occurring events immediately without having to recompute the schedule for the entire time horizon but instead do batchwise assignment. Proposed method was validated by comparing it with the baseline greedy method and a modified version of the baseline called Priority greedy method. The assignment of personnel by the proposed method resulted in a reduction in average service time of events for large scenarios compared to that of the other two methods and was able to provide solution in a reasonable time. The proposed method increases the efficiency of providing services by reducing the associated risk.

The problem of scheduling and routing tree construction in WiMAX/802.16 based mesh networks is not defined in the standard and has thus been the subject to extensive research. We consider the problem of joint routing and scheduling in WiMAX-based mesh networks, with the objective of determining a minimum schedule period that satisfies a given (uplink/downlink) traffic demand. Minimizing the length of a schedule amounts to maximizing the spectrum spatial reuse by activating concurrently as many links. This group of transmission links active concurrently is referred to as the transmission group and refers to the set of wireless links that can simultaneously transmit without violating the signal-to-interference-plus-noise ratio (SINR) requirement. Our model is referred to as maximum spatial reuse (MSR). We assume centralized scheduling at the base station and attempt to maximize the system throughput through appropriate routing tree selection and achieving efficient spectrum reuse through opportunistic link scheduling. We present an ILP optimization model for the joint problem, which relies on the enumeration of all possible link schedules. Given its complexity, we decompose the problem using a column generation (CG) approach. We present two formulations for modeling MSR, namely the link-based (CGLink) and the path-based (CGPath) formulation. These two formulations differ mainly in the number of routing decision variables. Our experimental results indicate that the path-based formulation needs much less computational (CPU) time than the link-based in order to determine the (same) optimal solution with the same spatial reuse gain.

The literature on programming sensor networks has focused so far on providing higher-level abstractions for expressing local node behavior. Kairos is a natural next step in sensor network programming in that it allows the programmer to express, in a centralized fashion, the desired global behavior of a distributed computation on the entire sensor network. Kairos’ compile-time and runtime subsystems expose a small set of programming primitives, while hiding from the programmer the details of distributed-code generation and instantiation, remote data access and management, and inter-node program flow coordination. In this paper, we describe Kairos’ programming model, and demonstrate its suitability, through actual implementation, for a variety of distributed programs—both infrastructure services and signal processing tasks—typically encountered in sensor network literature: routing tree construction, localization, and object tracking. Our experimental results suggest that Kairos does not adversely affect the performance or accuracy of distributed programs, while our implementation experiences suggest that it greatly raises the level of abstraction presented to the programmer.

Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged in a particular order in each Virtual Channel (VC). This implementation is vulnerable to HoL blocking, as the switch allocator can allocate only those packets which are available at the head in a VC. In this paper, Swapped Buffer (SB) Router architecture is proposed to schedule packets in input buffers by using SB registers. The VCs are designed as SBs, this allows the packets stored in SB registers along with the head packet of VC to participate in SA. The concept of the SB register minimizes the conflicts in SA and thus reduces HoL blocking, therefore improves the performance of NoC. This paper proposes a priority mechanism to prioritize the non-head packets as compared to head packets in case of conflict between them. Two methods have been proposed in this paper, to enhance the performance of the NoC router. First, a VC allocation technique is proposed to optimize the order of packets in the input buffer. Next, SB-Router is combined with the Fill VC allocation technique to further enhance the performance of NoC routers. The performance of the proposed router is evaluated and the experimental results indicate that our design achieves latency improvement of 68.75% over (Time-Series) TS-Router for uniform traffic at the injection rate of 0.42 flits/cycle for a 64 node mesh network with moderate power consumption and area usage. The performance improvement in packet latency for traces from Princeton Application Repository for Shared-Memory Computers (PARSEC) has also been evaluated. With the achieved reduction in latency, the proposed method has the potential to serve high-speed operations while mapping different applications on multiple core architectures.

This paper proposes a minimum-width multi-row transistor placement method for CMOS cells in presence of non-dual P and N type transistors. This is the first exact multi-row transistor placement method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. Moreover, the proposed method uses more efficient gate connection style, and generates more area-efficient transistor placements than the conventional method. Experimental results show that the proposed method can generate the minimum width multi-row transistor placement of the cells with up to 26 transistors in reasonable time.

A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor level circuit simulator allows efficient invocation of the simulation.

In recent years, wireless sensor networks have been used for various applications such as environmental monitoring, military and medical applications. A wireless sensor network uses a large number of sensor nodes that continuously collect and send data from a specific region to a base station. Data from sensors are collected from the study area in the common scenario of sensor networks. Afterward, sensed data is sent to the base station. However, neighboring sensors often lead to redundancy of data. Transmission of redundant data to the base station consumes energy and produces traffic, because process is run in a large network. Data aggregation was proposed in order to reduce redundancy in data transformation and traffic. The most popular communication protocol in this field is cluster based data aggregation. Clustering causes energy balance, but sometimes energy consumption is not efficient due to the long distance between cluster heads and base station. In another communication protocol, which is based on a tree construction, because of the short distance between the sensors, energy consumption is low. In this data aggregation approach, since each sensor node is considered as one of the vertices of a tree, the depth of tree is usually high. In this paper, an efficient hierarchical hybrid approach for data aggregation is presented. It reduces energy consumption based on clustering and minimum spanning tree. The benefit of combining clustering and tree structure is reducing the disadvantages of previous structures. The proposed method firstly employs clustering algorithm and then a minimum spanning tree is constructed based on cluster heads. Our proposed method was compared to LEACH which is a well-known data aggregation method in terms of energy consumption and the amount of energy remaining in each sensor network lifetime. Simulation results indicate that our proposed method is more efficient than LEACH algorithm considering energy consumption.

Topological analysis is used in several domains to identify and characterize important features in scientific data, and is now one of the established classes of techniques of proven practical use in scientific computing. The growth in parallelism and problem size tackled by modern simulations poses a particular challenge for these approaches. Fundamentally, the global encoding of topological features necessitates interprocess communication that limits their scaling. In this paper, we extend a new topological paradigm to the case of distributed computing, where the construction of a global merge tree is replaced by a distributed data structure, the merge forest, trading slower individual queries on the structure for faster end-to-end performance and scaling. Empirically, the queries that are most negatively affected also tend to have limited practical use. Our experimental results demonstrate the scalability of both the merge forest construction and the parallel queries needed in scientific workflows, and contrast this scalability with the two established alternatives that construct variations of a global tree.

We propose a low-voltage, low-current interconnect architecture using buffered/pipelined spin-torque (ST) sensors to optimize the overall delay and energy consumption. Conventional techniques for reducing energy consumption on long interconnects involve low voltage swings on interconnects or current-mode interconnects. However, such techniques require power-consuming voltage converters or trans-impedance amplifiers at the receivers. ST-sensor-based receivers have recently been introduced that can operate without analog components at the receiver. As a result, the energy consumption is lower compared to existing techniques. However, the delay can be relatively high in these networks for long Cu-lines since these methods do not accommodate conventional buffering schemes for delay minimization. Here, we propose the use of ST buffers in the line in addition to ST-sensing at the receiver. The buffers and sensors used in our design consist of a magnetic strip of two magnetic domains separated by a domain wall. The domain wall can be moved by a current flowing through an adjacent spin-Hall metal which leads to a change in the resistance of the receiver. This resistance change is easily sensed using simple CMOS components. With the introduction of buffering for ST-sensor interconnects, the proposed method can be highly efficient in optimizing the energy-delay performance for long, global on-chip or off-chip lines. Our simulation results indicate that for a 10 mm line in 45 nm CMOS technology, the energy consumption with ST-sensing is about 2 percent that of full-swing, and about 4 percent that of low-swing, CMOS interconnects. Moreover, the delay is much lower than low-swing, and comparable to full-swing, CMOS designs.