FAR

The first stage in channel routing is that of computing a routing solution S, for a given channel with as few tracks as possible. We consider a second stage in which it is desirable to reduce the total wire length without increasing area of routing. In this paper we propose efficient polynomial time algorithms for appreciably reducing the total wire length in two-, three- and multi-layer routing solutions by permuting tracks in the solution S obtained in the first stage. This results in a routing solution that is economical in terms of area as well as total wire length. Our algorithms are particularly important in practical terms since the problem of minimizing the total wire length in a routing solution is NP-hard.

In the routing design of interposer and etc., the combination of a pin pair to be connected by wire is often flexible, and the reductions of the total wire length and the length difference are pursued to keep the circuit performance. Even though the total wire length can be minimized by finding a minimum cost maximum flow in set pair routing problems, the length difference is often large, and the reduction of it is not easy. In this paper, an algorithm that reduces the length difference while keeping the total wire length small is proposed. In the proposed algorithm, an initial routing first obtained by a minimum cost maximum flow. Then it is modified to reduce the maximum length while keeping the minimum total wire length, and a connection of the minimum length is detoured to reduce the length difference. The effectiveness of the proposed algorithm is confirmed by experiments.

Consider a set of n pins and $n( n - 1 )/2$ specified numbers of wire connections between all pairs of the n pins There are also n holes all in a line with adjacent holes at unit distances apart. The problem is to put the n pins into the n holes such that the total wire length is a minimum. We can abstract the pins and wire connections as a graph G with n nodes and numbers associated with the arcs. For an arbitrary G, we establish a lower bound on the total wire length. If G is a rooted tree, an algorithm is presented which requires $O( {n\log n} )$ operations.

Koch fractal monopole antennas are known to exhibit lower resonant frequencies than Euclidean monopoles of the same height. It has been concluded that there exists a unique relationship between the antenna's fractal geometry and its electromagnetic behavior. Here, the performance properties of the Koch fractal monopole are examined and compared with the performance properties of other bent wire geometry monopoles having the same total wire length and overall height. It is demonstrated that monopoles with less complex shapes exhibit lower resonant frequencies because they are more effective at increasing the electrical volume of the antenna. When these antennas are made to be resonant at the same frequency, they exhibit virtually identical performance properties independent of differences in their geometric shape and total wire length. It is also demonstrated that the effective height of these monopoles converge to that of an electrically small Euclidean monopole near the small antenna limit and they exhibit virtually identical radiation resistance properties at low frequencies. Finally, it is shown that the fractal limit in lowering of resonant frequency is related to the limit in the increase in the antenna's effective volume.

The resonant properties of several small planar space-filling fractal antennas are considered over a range of self-resonant frequencies. These space-filling antennas have differing geometries and total wire length, but occupy the same planar area. The resonant properties considered include radiation resistance, efficiency, and quality factor. It is demonstrated that the resonant properties of these antennas are essentially the same, independent of significant differences in antenna geometry and total wire length.

In this paper, we present TQPF, a Timing-Driven Quadratic-based Placement Tool for FPGAs. Quadratic placement algorithms try to minimize total squared wire length by solving linear equations. The resulting placement tends to locate all cells near the center of the chip with a large amount of overlap. Also, since squared wire length is only an indirect measure of linear wire length, the resulting total wire length may not be minimized. We propose methods to alleviate the above two problems that give high-quality results while minimizing the total run time. We incorporate multiple iterations of equation-solving process together with a technique for pulling nodes out of the dense area while minimizing linear wire length. Experimental results using 20 Microelectronics Center of North Carolina (MCNC) benchmark circuits show that, on average, TQPF is approximately three times faster than the well-known Versatile Placement and Routing tool for FPGAs (VPR). The estimated total wire length, on average, is only 1.4% longer, and the critical path delay is 4.9% lower.

Channel routing problem of area minimization is a well-defined problem in VLSI physical design automation. In this paper we have developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions. Here we consider the total wire length of a routing solution as one of the most important factors of high performance computing. Reduction in wire length is important from signal delay as well as from the viewpoint of cost of wire segments required in interconnecting all the nets. The framework is designed for computing routing solutions in two-layer channels, and extended to route three-layer routing also in a modular fashion. All the algorithms developed under the framework of TAH are executed for computing no-dogleg and dogleg routing solutions for most of the well-known benchmark channels, with reduced total area and/or total wire length in two- and three-layer channel routing. Performance of our algorithms is highly encouraging.

The quality of the clock distribution networks (CDNs) impacts the performance of an SoC. In this paper, we propose local topology modification (LTM) in order to enhance the CDN's quality in terms of total wire length and wire elongations. The incorporation of this method into a deferred-merge embedding algorithm (DME) and greedy-DME (GDME) reduces the total wire length by around 7.83% and 9.77% respectively, with a slight increase in run time. In addition, we show that GDME relies intensively on wire elongations and it offers a solution that suffers from high standard deviation of the path lengths between clock pins and the CDN's root (SDPL). Applying LTM to GDME reduces wire elongations and SDPL by 96.4 % and 51.5 % respectively.

Neural systems are shaped by multiple constraints, balancing region communication with the cost of establishing and maintaining physical connections. It has been suggested that the lengths of neural projections be minimized, reducing their spatial and metabolic impact on the organism. However, long-range connections are prevalent in the connectomes across various species, and thus, rather than rewiring connections to reduce length, an alternative theory proposes that the brain minimizes total wiring length through a suitable positioning of regions, termed component placement optimization. Previous studies in nonhuman primates have refuted this idea by identifying a nonoptimal component placement, where a spatial rearrangement of brain regions in silico leads to a reduced total wiring length. Here, for the first time in humans, we test for component placement optimization. We show a nonoptimal component placement for all subjects in our sample from the Human Connectome Project (N = 280; aged 22–30 years; 138 females), suggesting the presence of constraints—such as the reduction of processing steps between regions—that compete with the elevated spatial and metabolic costs. Additionally, by simulating communication between brain regions, we argue that this suboptimal component placement supports dynamics that benefit cognition.

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. Therefore, it is very important to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

This paper presents a new detialed router for the hierarchical field programmable gate arrays (H-FPGAs). The optimal objectives of proposed routing algorithm are improving the time consumption of routing procedure (minimizing the running time of algorithm), and at the same time make great effort to decrease the wire length and critical path delay. Initially, nets are routed sequentially according to their criticalities. Then, to achieve optimization targets, the nets violating routablity constrains are resolved iteratively by a rip-up and rerouting router using the simulated evolution optimization technique, where each net will be evaluated via a rip-up priority function consisting of the timing part and the congestion part, and then compared to a random number to decide if it will be ripped and rerouted. An experimental result under commercial H-FPGA shows that our router can have about 26% improvement on the time-consumption and 0.45% reduction on total wire length when compared with a modified VPR.

As devices and lines shrink into the deep submicron range, the propagation delay of signals can be effectively improved by repowering the signals using intermediate buffers placed within the routing trees. Almost no existing timing driven floorplanning and placement approaches consider the option of buffer insertion. As such, they may exclude solutions, particularly early in the design process, with smaller overall area and better routability. In this paper, we propose a new methodology in which buffered trees are used to estimate wire delay during floorplanning. Instead of treating delay as one of the objectives, as done by the majority of previous work, we formulate the problem in terms of delay bounded buffered trees (DBB-tree) and propose an efficient algorithm to construct a DBB spanning tree for use during floorplanning. Experimental results show that the algorithm is very effective. Using buffer insertion at the floorplanning stage yields significantly better solutions in terms of both chip area and total wire length.

This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). The average edge reduction of 9.3% is achieved while maintaining depth and LUT count of state-of-the-art technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wire length, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth. The percentages of 5- and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual output LUT structure found in commercial FPGAs. WireMap leads to 9.4% fewer dual-output LUTs after merging

Macroblock pin assignment and routing are important tasks in physical design. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing and 2) a net-by-net approach where pin assignment and routing for a single net are performed simultaneously. However, none of the existing algorithms is "exact" in the sense that they may fail to route all of the nets even though a feasible solution exists. This remains to be true even if only two-pin nets with fixed pins between two blocks are concerned. In this paper, we consider the problem of two-pin net connections from one macroblock to all of the other blocks, and present the first polynomial-time exact algorithm for simultaneous pin assignment and routing for all of the two-pin nets between one block (source block) and all of the other blocks. In addition to finding a feasible solution whenever one exists, it guarantees to find a pin-assignment/routing solution with minimum cost /spl alpha//spl middot/W+/spl beta//spl middot/V, where W is the total wire length and V is the total number of vias. Our algorithm has various applications. 1) It is suitable in engineering change order (ECO) situations where the existing solution is modified incrementally. 2) Given any pin assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. Furthermore, it provides an efficient algorithm for the pin assignment and routing problem of all of the blocks. The method is applicable to both global and detailed routing with arbitrary routing obstacles on multiple layers. Experimental results demonstrate its efficiency and effectiveness.

This paper addresses a placement method good for module generation. Conventional partitioning based method can not guarantee the best quality in consecutive partitioning, even if it can find a sequence of the minimum partitioning of a circuit into two subcircuits. Also, when size of cells varies very much, which is often seen in module generation as leaf cells, it is sometimes too strong constraint for them to get the minimum partitioning under ``partitioning into two similar size of subcircuits''. On the other hand, although conventional Simulated Annealing (SA) based method gives a better result, it requires extremely long computation time, since they do not employ any divide and conquer technique. It is the purpose of this paper to propose an algorithm which is based on SA method and employs the divide and conquer technique so that it gives better quality than partitioning based method and also it gives drastically faster computation time than SA method. As the first step, we applied this idea to the linear placement. Our algorithm is based on sorting inside subgroups, and this subgroup generation is done by plural cut-lines with a constant pitch. This constant pitch will be decreased from sufficiently large value to small value gradually, and this decreasing schedule is similar to the cooling schedule of SA method. And also, since there is a variation of offset in applying cut-lines even with the same pitch value, we randomly select one of them like SA method chooses a pair of components to be switched at random. Sorting inside subgroups is only a rearrangement depending on the connection between subgroups and is very fast. It is found that the total wiring length is improved about 10% compared to that of spectral method which was recognized to be the best (SLPC2). Also, computation time was dramatically reduced over the SA method.