A Hexagon-Based Honeycomb Routing Architecture for FPGA

As modern FPGAs continue to scale, the routing architecture increasingly dominates both area and delay. However, traditional homogeneous routing architectures struggle to efficiently accommodate spatially varying routing demands, often resulting in imbalanced routing resource utilization across different regions. This inefficiency contributes to increased routing area and critical path delay (CPD). To address this limitation, this paper proposes a hybrid FPGA routing architecture that introduces spatial heterogeneity into interconnect block configurations. The proposed architecture is fully parameterized, allowing different regions of the FPGA fabric to adopt distinct routing topologies tailored to local connectivity requirements. To support this architecture within the Verilog-to-Routing (VTR) toolchain, we extend the architecture description file format and enhance the routing resource graph (RRG) generator to support region-specific interconnect features. Furthermore, to efficiently search the vast parameter space, we employ a parallel Bayesian optimization (BO)-based design space exploration (DSE) framework for automated identification of optimal architecture configurations. Experimental results on the VTR benchmark suite demonstrate that the proposed hybrid routing architecture achieves up to 7.9% reduction in routing area, 2.5% improvement in CPD, and 10.1 % improvement in area-delay product (ADP) compared to the state-of-the-art VIB architecture. Additional analysis also shows a 38.09 % reduction in routing detour, confirming the effectiveness of the hybrid architecture in improving routing compactness and reducing wire overhead.

Due to the rapid growth in the size of designs and Field Programmable Gate Arrays (FPGAs), CAD run-time has increased dramatically. Reducing FPGA design compilation times without degrading circuit performance is crucial. In this work, we describe a novel approach for incremental design flows that both identifies tightly grouped FPGA logic blocks and then uses this information during circuit placement. Our approach reduces placement run-time on average by more than 17% while typically maintaining the design's critical path delay and marginally increasing its minimum channel width and wire length on average. Instead of following the traditional approach of evaluating a circuit's pre-placement netlist, this new algorithm analyzes designs post-placement to detect proximity data. It uses this information to non-aggressively extract heterogeneous cluster groupings from the design, which we call gems, that consist of two to seventeen clusters. We modified VPR's simulated annealing placement algorithm to use our Singularity Placer, which first crushes each cluster grouping into a singularity, to be treated as a single cluster. We then run the annealer over this condensed circuit, followed by an expansion of the singularities, and a second annealing phase for the entire expanded circuit.

In the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it. In a recent work by Hoo et al., the authors have developed a linear programming (LP)-based framework that parallelizes this routing process to achieve significant speed-ups (the resulting algorithm is termed as ParaLaR). However, this approach has certain weaknesses. Namely, the constraints violation by the solution and a standard routing metric could be improved. We address these two issues here. In this paper, we use the LP framework of ParaLaR and solve it using the primal–dual sub-gradient method that better exploits the problem properties. We also propose a better way to update the size of the step taken by this iterative algorithm. We call our algorithm as ParaLarPD. We perform experiments on a set of standard benchmarks, where we show that our algorithm outperforms not just ParaLaR but the standard existing algorithm VPR as well. We perform experiments with two different configurations. We achieve 20 % average improvement in the constraints violation and the standard metric of the minimum channel width (both of which are related) when compared with ParaLaR. When compared to VPR, we get average improvements of 28 % in the minimum channel width (there is no constraints violation in VPR). We obtain the same value for the total wire length as by ParaLaR, which is 49 % better on an average than that obtained by VPR. This is the original metric to be minimized, for which ParaLaR was proposed. Next, we look at the third and easily measurable metric of critical path delay. On an average, ParaLarPD gives 2 % larger critical path delay than ParaLaR and 3 % better than VPR. We achieve maximum relative speed-ups of up to seven times when running a parallel version of our algorithm using eight threads as compared to the sequential implementation. These speed-ups are similar to those as obtained by ParaLaR.

Modern FPGAs utilize complex routing architectures to optimize the area, critical path delay, and power consumption. General Routing Block (GRB) models the routing resources of modern FPGAs, enabling the design of better routing architectures than previous academic FPGAs based on the CB-SB model. However, the design space of the GRB model is too large to be explored manually. In this paper, we propose GRAEBO, a design space exploration (DSE) algorithm for FPGA routing architectures based on Bayesian optimization, which can optimize and accelerate the DSE by balancing exploration and exploitation. Moreover, we design pruning rules to further improve the DSE efficiency, which can serve as a multi-fidelity acceleration method. GRAEBO obtains better area, delay, and area-delay product than a 142-channel baseline CB-SB architecture, with improvements of 8%, 19%, and 26%, respectively. Compared to the GRB architecture found by the simulated annealing algorithm, GRAEBO achieves 9% smaller area, 5% shorter delay, and 13% better area-delay product on the VTR benchmarks.

Field Programmable Gate Arrays (FPGAs) have become a popular medium for the implementation of many digital circuits. Mapping applications into FPGAs requires a set of efficient Computer-Aided Design (CAD) tools to obtain high-quality Integrated Circuits (ICs). One critical issue of FPGA implementation is the quality and efficiency of associated CAD algorithms. In this paper, we are interested in investigating clustering algorithms aspect to optimize Mesh of Clusters (MoCs) FPGA performance. In fact, the way we distribute Logic Blocks (LBs) between FPGA clusters has an important impact on performance. In this paper, we explore the effects of two clustering algorithms (First Choice (FC) and T-VPack) on MoCs FPGA architecture based only on short routing wires. This paper highlights and experimentally demonstrates that FC clustering algorithm ameliorates power consumption, area, critical path delay and energy by an average of 17%, 11%, 13% and 24% respectively compared to T-VPack for MoCs FPGA.

In this article, an area-efficient VLSI architecture scheme for high-throughput computation of the 2-D discrete wavelet transform (DWT) is proposed, effectively applied in the context of aircraft cargo hold scenes. The proposed architecture aims to reduce computation and storage resources while maintaining the DWT-IDWT reconstructed image quality for the 9/7 discrete wavelet. The hardware implementation formulae based on the flipping architecture have been modified to reduce RAM storage bit width. By transforming the coefficients of the formula into hardware-friendly values, the required multiplication operations are split into two stages of addition. On this basis, a pipelined architecture is constructed to set the critical path delay (CPD) of the architecture to be close to the delay of a single adder, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{a}$ </tex-math></inline-formula>, thereby achieving a high throughput. Compared to existing architectures in the research field, the proposed single-level 2-D DWT architecture achieves resource savings on the field-programmable gate array (FPGA) platform while ensuring good image reconstruction quality. The advantages of the multilevel 2-D DWT are even more pronounced. In the simulation results on the application-specific integrated circuit (ASIC) platform, the proposed architecture reduces computation time by at least 35.54% while achieving a higher level of decomposition, decreases the area-delay product (ADP) by at least 25.41%, and saves a significant amount of energy per image (EPI). Furthermore, the proposed folded architecture achieves close to 100% hardware utilization efficiency (HUE) in multilevel 2-D DWT computations.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

In recent years, Spiking Neural Networks (SNNs) have been increasingly deployed on Field Programmable Gate Arrays (FPGAs) for enabling low-energy AI inference. SNNs aim to enable more biomimetic processing than ANNs, thereby enabling more event-driven computing along with using cheaper arithmetic than multiply and accumulate operations. However, deploying large SNNs to achieve acceptable accuracy requires extensive use of configurable logic blocks (CLBs), leading to additional programmable routing and critical path delay. This study addresses these issues by exploring soft-logic architectures to reduce resource utilization for SNNs. We propose two architectures that provide a more efficient mapping of logic primitives for SNNs, reducing CLB usage by 13.49% and 20.13% compared to the Intel Stratix10 baseline. Implemented with an advanced technology node, these architectures achieve an average reduction of 8.30% and 7.30% in CLB area and reduce critical path delay by 2.72% and 3.42%, respectively, enabling larger SNNs with faster inference within the same programmable fabric.

This paper describes a new detailed routing algorithm, specially designed for those architectures that are found in most recent generations of Field-Programmable Gate Arrays (FPGAs). The algorithm also brings a solution for those architectures where multiplexed switches are used in order to decrease the chip area like the recently proposed FIPSOC FPGA. The algorithm, called RAISE, can be applied to a broad range of optimization problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels, with or without the use of multiplexed switches. RAISE (Router using Adaptive Simulated Evolution) searches not just for a possible solution, but tries to find the one with minimum delay. Excellent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.

Field programmable gate array (FPGA) devices are highly susceptible to transistor aging, mainly through the bias temperature instability (BTI) phenomenon. BTI can be modeled as threshold voltage increase in MOSFET transistors, which leads to the degradation in device performance. As technology scales, leakage power has turned into a major portion of FPGA total power consumption. In this paper, we study the mutual effects of BTI and leakage power by considering the temperature changes in the basic components of FPGAs. Our analysis shows that while the leakage-power reduction caused by BTI may be considered desirable, a bit-flipping scheme should still be employed to mitigate device degradation. We present an optimization problem to optimize the device performance over the device's lifetime. A postrouting aging-aware timing analysis method is also proposed to find the best flipping frequency. The simulation results show that bit flipping at a proper frequency may reduce the power consumption of device by about 5% while keeping the critical path delay below a given constraint.

A Field Programmable Gate Array (FPGA) consists of an array of identical configurable logic blocks (CLBs), each capable of implementing any boolean function with a bounded number of inputs. Such architectural regularity provides an inherent redundancy which can be exploited for fault tolerance and yield enhancement. In this paper we examine the problem of reconfiguring the placement of a circuit on an FPGA to tolerate a given fault pattern in the array of CLBs. The primary objective of the placement reconfiguration is to minimize timing degradation. The secondary objective is to minimize the amount of re-programming (both in the CLBs and in the routing switches) in the reconfiguration process. The concept of a slack neighborhood graph is introduced as a general tool for timing driven reconfiguration with a bounded increase in critical path delay. Our algorithm simultaneously achieves both provably low timing degradation and low reprogramming cost. Slack neighborhood graphs are of independent interest due to their possible applications to the timing driven placement problem. For a wide range of fault probabilities and circuits our algorithm successfully reconfigures the placement with less than 1% degradation in the circuit delay.

Traditional Field Programmable Gate Array (FPGA) based Advanced Encryption Standard (AES) architectures usually suffer from dynamic power consumption due to parallel S-box operations in the SubBytes transformation. To overcome this issue, a finite state machine (FSM) controlled Split SubBytes AES 128 architecture was introduced and synthesized on Zynq 7000 ZC702 Evaluation Board (xc7z020clg484-1) FPGA using Vivado v.2024.2 tool in which eight S-boxes reused over two sequential subcycles achieving 6.107 ns critical path delay, 22% power reduction and 163.7 MHz operating frequency compared with the traditional AES core. The comparative evaluation with existing works confirm that proposed FSM based architecture offers an effective power and performance trade-offs and the fault tolerant design maintains timing with 28% power overhead ensuring balance between efficiency and reliability.

The large arithmetic-intensive applications increasingly implemented on field-programmable gate arrays (FPGAs) challenge FPGA architects to design FPGAs that can efficiently transport large amount of multi-bit wide signals in the data-path circuits of these applications. In this work, we investigate the area efficiency of two FPGA multi-bit aware routing architectures - the sparse and the enhanced sparse architectures, and compare them with the conventional and the configuration memory sharing architectures. We found that the sparse and enhanced sparse architectures are 6-10% more efficient than the conventional architecture. Our data also show that while the configuration memory sharing architecture can achieve the highest level of theoretical area savings for multi-bit transportation, it performs poorly for circuits with 50% or less multi-bit signals. These results suggest that FPGA architects should look beyond conventional architectures in order to create more efficient routing architectures for modern FPGAs.

Field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gate arrays. Hierarchical interconnection structures for field programmable gate arrays are proposed. They help overcome these problems. Logic blocks in a field programmable gate array are grouped into clusters. Clusters are then recursively grouped together. To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed. The field programmable gate arrays with new architecture can be efficiently configured with existing computer aided design algorithms. The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously. Experiments on benchmark circuits show that density and performance are significantly improved.

The authors explore and design the traditional field-programmable gate array (FPGA) interconnect topologies and architectures that can play an important role in improving performance and density. The main architectures under exploration are tree-based and island-style Manhattan Mesh. Mesh-based design is the most common industrial and academic architecture. Numerous research and industrial designs have been developed to improve mesh-based FPGAs' performance, area, and power consumption. Nonetheless, when looking at performance metrics such as speed, area, and power, the gap is generally very wide for FPGAs compared to application-specific integrated circuits (ASICs). Despite their good properties, such as high logic density and area advantage, tree-based architectures have been overlooked up to now. This article addresses long wire length issues associated with tree-based programmable interconnects using 3D design and manufacturing technologies. Using their dedicated 3D design and optimization methodology, the authors show that 3D tree-based architecture is 1.5 times faster than the mesh-based counterpart.