GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization

As modern FPGAs continue to scale, the routing architecture increasingly dominates both area and delay. However, traditional homogeneous routing architectures struggle to efficiently accommodate spatially varying routing demands, often resulting in imbalanced routing resource utilization across different regions. This inefficiency contributes to increased routing area and critical path delay (CPD). To address this limitation, this paper proposes a hybrid FPGA routing architecture that introduces spatial heterogeneity into interconnect block configurations. The proposed architecture is fully parameterized, allowing different regions of the FPGA fabric to adopt distinct routing topologies tailored to local connectivity requirements. To support this architecture within the Verilog-to-Routing (VTR) toolchain, we extend the architecture description file format and enhance the routing resource graph (RRG) generator to support region-specific interconnect features. Furthermore, to efficiently search the vast parameter space, we employ a parallel Bayesian optimization (BO)-based design space exploration (DSE) framework for automated identification of optimal architecture configurations. Experimental results on the VTR benchmark suite demonstrate that the proposed hybrid routing architecture achieves up to 7.9% reduction in routing area, 2.5% improvement in CPD, and 10.1 % improvement in area-delay product (ADP) compared to the state-of-the-art VIB architecture. Additional analysis also shows a 38.09 % reduction in routing detour, confirming the effectiveness of the hybrid architecture in improving routing compactness and reducing wire overhead.

Approximate computing has emerged as a promising solution in energy-efficiency applications. Recently, attention has shifted from approximate components to Design Space Exploration (DSE) algorithms. However, traditional DSE algorithms face challenges in efficiently obtaining optimal solutions within large and complex design spaces. This paper introduces a prerefining enhanced design space exploration framework that provides customized design space and cost-performance formula for applications. Experimental results demonstrate that integrating this pre-refining step into various DSE algorithms leads to substantial performance gains, including up to $87 \times$ speedup and a 23% improvement in hardware overhead. Moreover, the innovative cost-performance-based DSE algorithm attains a $7.7 \times$ acceleration and further optimizes hardware metrics by an additional 8.8% compared to advanced frameworks employing the same pre-refinement.

This paper describes a novel and fast placement algorithm for FPGA design space (e.g., area, power or reliability) exploration. The proposed algorithm generates the placement based on the topological similarity between two configurations (netlists) in the design space. Thus, it utilizes the sharing of reusable information during the design space exploration and avoids the time-consuming placement computation like VPR. Tested on logic-level and algorithm-level design space exploration cases, our similarity-based placement accurately depicts the “shape” of a design space and pinpoints the designs which are of most interest to IC designers. Moreover, a turbo version of circuit similarity-based placement performs an average of 30x (up to 100x) faster than VPR's while still achieving comparable placement results.

A major challenge in the model‐based engineering of Cyber‐Physical Systems (CPSs) is that of providing methods and tools that support decision‐making in design. In the CPS design space, system models may be composed of diverse notations and tools, and the range of alternatives to be evaluated is immense. In spite of this, the benefits of trade‐off analysis at an early design stage are significant, making the automation of Design Space Exploration (DSE) an appealing prospect. In bringing DSE to industry scale, there is a clear need for both guidance to engineers in designing DSE, and a theory of cost‐effective DSE algorithms. To address this, we propose and demonstrate a SysML profile that encourages the explicit description of DSE over multi‐disciplinary co‐models, and demonstrate the ability to tune a genetic DSE algorithm across a range of design spaces.

Heterogeneous multiprocessor platforms are becoming widespread in the embedded system domain, mainly for the opportunity to improve timing performance and to minimize energy/power consumption and costs. Therefore, when using such platforms, it is important to adopt a Design Space Exploration (DSE) strategy that considers compromises among different objectives. Existing DSE approaches are generally based on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOPs) by minimizing a linear combination of weighted cost functions (i.e., Weighted Sum Method, WSM). In this way, the main issues are related to reduce timing execution while trying to improve the evolutionary algorithm performance, introducing strategies that attempt to bring better solutions. Code parallelization is one of the most used approaches in this field, but no standard methods have been released since different aspects could affect the performance. This approach leads to exploit parallel and distributed processing elements in order to implement evolutionary algorithms. In the latter case, if we consider genetic algorithms, it is possible to talk about Parallel Genetic Algorithms (PGA). Considering this context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an improvement that reduces execution time using parallel programming languages (i.e., OpenMP) inside the main genetic algorithm approach, while trying to lead to better partitioning solutions. The descriptions of the adopted DSE activities and the OpenMP implementation, validated by means of a case study, represent the core of the paper.

Field Programmable Gate Arrays (FPGAs) are widely used for their flexibility and short time to market. FPGA routing architecture design is the key problem due to the fact that it plays a dominant role in the area, delay and power. Most of modern FPGAs are island-style which provide abundant vertical and horizontal tracks to guarantee the circuit designs can be routed successfully. Most connections in placed netlists are diagonal which may lead to passing through extra turning switches, resulting in increased delay cost and high routing density. In this paper, we propose a hexagon-based honeycomb FPGA routing architecture to improve the routability and performance. In honeycomb architecture, there are three kinds of routing channels which can provide more freedom to decrease the turning switches on the routing paths. In addition, the router lookahead algorithm is enhanced to support the honeycomb architecture which is then evaluated by the enhanced VTR with provided benchmarks. The experimental results show that the honeycomb architecture can improve the minimum routing channel width by 7.7% compared with traditional rectangular architecture with length-1 wires. In addition, the honeycomb architecture can achieve 9.9% improvement on the routed wirelength, 11.5% on the critical path delay and 12.4% on the area-delay product.

This article presents a detailed overview and the experimental comparison of 15 multi-objective design-space exploration (DSE) algorithms for high-level design. These algorithms are collected from recent literature and include heuristic, evolutionary, and statistical methods. To provide a fair comparison, the algorithms are classified according to the approach used and examined against a large set of metrics. In particular, the effectiveness of each algorithm was evaluated for the optimization of a multiprocessor platform, considering initial setup effort, rate of convergence, scalability, and quality of the resulting optimization. Our experiments are performed with statistical rigor, using a set of very diverse benchmark applications (a video converter, a parallel compression algorithm, and a fast Fourier transformation algorithm) to take a large spectrum of realistic workloads into account. Our results provide insights on the effort required to apply each algorithm to a target design space, the number of simulations it requires, its accuracy, and its precision. These insights are used to draw guidelines for the choice of DSE algorithms according to the type and size of design space to be optimized.

In this work, we evaluate bi-directional and unidirectional FPGA routing architectures in terms of energy and power consumption using an updated power estimation framework compatible with VPR 5.0. The goal of this research is to help FPGA vendors find the best FPGA architectures. Initially, we make some general observations on how two types of routing architectures affect speed, area consumption, and power consumption. We observe how routing buffer sizing affects both the critical path delay and power and energy consumption of FPGAs with certain routing architectures. Our results show that uni-directional routing architecture, in all but one case, is the most energy efficient choice both in the traditional FPGA domain and the mobile domain where clock frequencies are fixed.

Design space exploration of microprocessor is still a challenging task for processor designers. Due to the huge design space, it is hard to determine the optimal configuration of microarchitecture parameters to satisfy the target performance and power requirements within limited time at the early stage of processor design. In this paper, a Critical Path Analysis directed Design Space Exploration (CPADSE) methodology for design space exploration of microprocessors is proposed. In CPADSE, a dependence graph model is constructed using the profile information generated during the program simulation. Then the critical paths of the dependence graph model are computed and patterns of the critical path are identified. The microarchitecture parameters mostly affecting processor`s performance or other metrics can be identified using the Plackett-Burman design method, which is always referenced as sensitivity analysis. Then the result of critical path analysis and sensitivity analysis is further used to guide the selection of search direction in both SA-CPADSE and TB-CPADSE design space search algorithms, which are proposed in this paper. Experiment result shows that for the design space exploration on SPEC 2000 benchmarks, SA-CPADSE obtains 2x speedup over baseline design space exploration algorithm SA-DSE. Additionally, TB-CPADSE on average obtains 4.3x speedup over SA-CPADSE and 7x speedup over SA-DSE. At the end of this paper, we have a detailed discussion about how to extend CPADSE methodology to design space exploration of multicore processors.

Due to the large number of optimizations provided in modern compilers and to compiler optimization specific opportunities, a Design Space Exploration (DSE) is necessary to search for the best sequence of compiler optimizations for a given code fragment (e.g., function). As this exploration is a complex and time consuming task, in this paper we present DSE strategies to select optimization sequences to both improve the performance of each function and reduce the exploration time. The DSE is based on a clustering approach which groups functions with similarities and then explore the reduced search space provided by the optimizations previously suggested for the functions in each group. The identification of similarities between functions uses a data mining method which is applied to a symbolic code representation of the source code. The DSE process uses the reduced set identified by clustering in two ways: as the design space or as the initial configuration. In both ways, the adoption of a pre-selection based on clustering allows the use of simple and fast DSE algorithms. Our experiments for evaluating the effectiveness of the proposed approach address the exploration of compiler optimization sequences considering 49 compilation passes and targeting a Xilinx MicroBlaze processor, and were performed aiming performance improvements for 41 functions. Experimental results reveal that the use of our new clustering-based DSE approach achieved a significant reduction on the total exploration time of the search space (18x over a Genetic Algorithm approach for DSE) at the same time that important performance speedups (43% over the baseline) were obtained by the optimized codes.

Exploration with a generative formalism must necessarily account for the nature of interaction between humans and the design space explorer. Established accounts of design interaction are made complicated by two propositions in Woodbury and Burrow's Keynote on design space exploration. First, the emphasis on the primacy of the design space as an ordered collection of partial designs (version, alternatives, extensions). Few studies exist in the design interaction literature on working with multiple threads simultaneously. Second, the need to situate, aid, and amplify human design intentions using computational tools. Although specific research and practice tools on amplification (sketching, generation, variation) have had success, there is a lack of generic, flexible, interoperable, and extensible representation to support amplification. This paper addresses the above, working with design threads and computer-assisted design amplification through a theoretical model of dialogue based on Grice's model of rational conversation. Using the concept of mixed initiative, the paper presents a visual notation for representing dialogue between designer and design space formalism through abstract examples of exploration tasks and dialogue integration.

All computing platforms, from mobile to supercomputers, are becoming more and more heterogeneous and massively parallel. While they can provide higher power efficiency and computation throughput, effective and confident use of these systems always requires knowledge about low-level programming. The average time necessary to develop and optimize a design on heterogeneous platforms is higher and higher compared to typical homogeneous systems. Dataflow models of computation (MoC) are quickly becoming the common practice in heterogeneous systems development. In domains such as signal processing and multimedia communication, dataflow MoCs have become accepted as standard. However, the shift from a sequential and architecture-specific MoC to a dataflow MoC still uncovers several programming and development challenges. The Cal Actor Language (CAL) is a recently-specified dataflow and actor-based language capable of concisely expressing complex and general purpose parallel applications. However, design tools supporting this language are generally not adequate to fully exploit its features and expressiveness power. In fact, they generally restrict its MoC in order to reduce the design space exploration (DSE) effort. The objective of this thesis is to provide a DSE methodology where all the features of CAL and dynamic dataflow MoCs can be exploited in a more general and effective manner. This dissertation illustrates a novel profiling, analysis and performance estimation methodology for the DSE of dynamic dataflow programs. The main research contributions of this thesis are: the formalization of a graph-based representation of the program execution called an execution trace graph (ETG); the formalization of a systematic methodology for profiling generic dynamic dataflow programs through their code interpretation; the formalization of a complete DSE methodology for dynamic dataflow programs in order to efficiently identify close-to-optimal design points according to various and tailored performance merit functions. In particular, the following design space optimization problems for dynamic dataflow programs are addressed: the analysis of the hotspots and the algorithmic bottlenecks of a parallel program; the bounding and optimization of the buffer size configuration for complex designs; the dynamic power dissipation minimization of programs implemented in multi-clock domain architecture. Furthermore, theoretical concepts like the design space critical path and the potential speedup of a dataflow application have been defined and revisited, respectively. The thesis also presents a DSE framework developed in order to demonstrate the effectiveness of this design methodology.

Bayesian optimization (BO) is a versatile and robust global optimization method under uncertainty. However, most of the BO algorithms were developed for problems with only continuous variables. For practical engineering optimization, discrete variables are also prevalent. BO methods based on Gaussian process (GP) surrogates also suffers from the curse-of-dimensionality problem. To address these challenges, in this paper, a Bayesian discrete optimization algorithm is introduced to solve permutation-based combinatorial problems. A new kernel function is developed based on position distances for permutation. To improve the efficiency and scalability of the algorithm, a sparse GP model based on inducing points is further developed, where the simulated annealing algorithm is applied to select inducing points. The new algorithm is demonstrated and tested with the production scheduling problem for additive manufacturing. Experimental results show that the proposed algorithm can find a better solution with limited evaluations than state-of-the-art algorithms.

The design of a complex embedded system is dominated by the definition of an optimal architecture in relation to certain performance indexes. This activity, known as design space exploration (DSE), is a great challenge for the EDA (electronic design automation) community. The enormous size of the design space, in fact, together with the long simulation time required to evaluate each system configuration during the exploration process, cause DSE to become a bottleneck in the design flow. In this paper we propose a multiobjective design space exploration methodology based on a genetic fuzzy system, the aim of which is to drastically reduce the exploration time while guaranteeing a high level of accuracy. The methodology uses a genetic algorithm (GA) for heuristic exploration and a fuzzy system to evaluate the configurations visited. Although of general application, the methodology is applied to a real case study: optimization of the performance and power consumption of an embedded architecture based on a very long instruction word (VLIW) microprocessor in a mobile multimedia application domain. The results obtained are compared, in terms of both accuracy and efficiency, with the state of the art in multiobjective DSE strategies, represented by the classical GA approach, demonstrating the scalability and effectiveness of the proposed approach.

Many demanding streaming applications share functional and structural similarities with other applications in their respective domain, e.g., video analytics, software-defined radio, and radar. This opens the opportunity for specialization to achieve the needed efficiency and/or performance.Platforms integrating many accelerators (ACCs) are a primary approach for efficient, high-performance stream computing. However, designing one platform for each application is not economical due to the high costs of nonrecurring engineering (NRE) and time-to-market (TTM). To this end, the concept of domain platforms is proposed, which takes advantage of similarities across applications and designs one unified platform to accelerate a domain of applications instead of focusing on a single reference application. This dissertation approaches designing domain platforms from a function-level (kernel-level) acceleration through a heterogeneous ACC-rich platform, where each ACC is specialized to accelerate a particular function. There is a great challenge to select ACCs allocated in the domain platform, considering the large design space and performance balance across many applications. However, current Design Space Exploration (DSE) tools only focus on an individual application in isolation (e.g., one particular vision flow) for allocating a platform, but not a set of similar applications. Multiple applications are only considered in the application bindings to an existing platform. Hence, optimizations that occur due to considering multiple applications simultaneously are missed in platform design. New DSE methodologies and tools are needed with a broader scope of application sets instead of individual applications. This dissertation introduces a novel Domain Design Space Exploration (DmDSE) methodology that broadens the DSE scope from an individual application to allocating a new heterogeneous ACC-rich platform for many applications.This dissertation defines domain characteristics to express the inherent structural and functional similarities across applications and metrics to quantitatively assess domain platforms with a balanced focus across various applications. Two novel algorithms, Dynamic Score Selection (DSS) and GenetIc Domain Exploration (GIDE), are introduced to do DmDSE and allocate domain platforms, which improve performance over application-specific platforms by 58% and 75% when only considering monolithic (single function) ACCs. A finer granularity of ACCs is beneficial for generality and performance under an area constraint. Considering multi-granularity similarities across functions, Multi-Granularity DmDSE (MG-DmDSE) extends DSE through allocating finer granular and configurable ACCs and decomposing functions in the binding. MG-DmDSE produces a more general platform that benefited 87.5% of applications, while only 50% from GIDE. With a huge design space, DmDSE suffers from a long exploration time due to a large number of complex platform evaluations. Heuristics and machine learning methods are proposed to speed up DmDSE.This dissertation introduces Greedy Guided Mutation (GGM) to speed up the mutation in the GIDE algorithm, which calculates an ACC score according to current allocation to guide mutation. Alternatively, Rapid Domain Platform Performance Prediction (RDP^3) methods are introduced to replace a large number of the slow platform assessment in domain DSE, which avoids the complex application binding exploration. In the experiments, GGM reduces 84.8% of exploration time with a 0.23% loss of the final OpenVX domain platform's performance. RDP^3, using a machine learning method, yields an even more significant speedup, saving 90.8% of exploration time with only 0.0003% performance loss. DmDSE is a milestone to broaden DSE scope from individual applications to the domain level. It tremendously pushes the domain platform design from an experience-guided, manual effort into an automated process.--Author's abstract