Analysis and optimization of dynamic dataflow programs

Design space exploration of microprocessor is still a challenging task for processor designers. Due to the huge design space, it is hard to determine the optimal configuration of microarchitecture parameters to satisfy the target performance and power requirements within limited time at the early stage of processor design. In this paper, a Critical Path Analysis directed Design Space Exploration (CPADSE) methodology for design space exploration of microprocessors is proposed. In CPADSE, a dependence graph model is constructed using the profile information generated during the program simulation. Then the critical paths of the dependence graph model are computed and patterns of the critical path are identified. The microarchitecture parameters mostly affecting processor`s performance or other metrics can be identified using the Plackett-Burman design method, which is always referenced as sensitivity analysis. Then the result of critical path analysis and sensitivity analysis is further used to guide the selection of search direction in both SA-CPADSE and TB-CPADSE design space search algorithms, which are proposed in this paper. Experiment result shows that for the design space exploration on SPEC 2000 benchmarks, SA-CPADSE obtains 2x speedup over baseline design space exploration algorithm SA-DSE. Additionally, TB-CPADSE on average obtains 4.3x speedup over SA-CPADSE and 7x speedup over SA-DSE. At the end of this paper, we have a detailed discussion about how to extend CPADSE methodology to design space exploration of multicore processors.

Many demanding streaming applications share functional and structural similarities with other applications in their respective domain, e.g., video analytics, software-defined radio, and radar. This opens the opportunity for specialization to achieve the needed efficiency and/or performance.Platforms integrating many accelerators (ACCs) are a primary approach for efficient, high-performance stream computing. However, designing one platform for each application is not economical due to the high costs of nonrecurring engineering (NRE) and time-to-market (TTM). To this end, the concept of domain platforms is proposed, which takes advantage of similarities across applications and designs one unified platform to accelerate a domain of applications instead of focusing on a single reference application. This dissertation approaches designing domain platforms from a function-level (kernel-level) acceleration through a heterogeneous ACC-rich platform, where each ACC is specialized to accelerate a particular function. There is a great challenge to select ACCs allocated in the domain platform, considering the large design space and performance balance across many applications. However, current Design Space Exploration (DSE) tools only focus on an individual application in isolation (e.g., one particular vision flow) for allocating a platform, but not a set of similar applications. Multiple applications are only considered in the application bindings to an existing platform. Hence, optimizations that occur due to considering multiple applications simultaneously are missed in platform design. New DSE methodologies and tools are needed with a broader scope of application sets instead of individual applications. This dissertation introduces a novel Domain Design Space Exploration (DmDSE) methodology that broadens the DSE scope from an individual application to allocating a new heterogeneous ACC-rich platform for many applications.This dissertation defines domain characteristics to express the inherent structural and functional similarities across applications and metrics to quantitatively assess domain platforms with a balanced focus across various applications. Two novel algorithms, Dynamic Score Selection (DSS) and GenetIc Domain Exploration (GIDE), are introduced to do DmDSE and allocate domain platforms, which improve performance over application-specific platforms by 58% and 75% when only considering monolithic (single function) ACCs. A finer granularity of ACCs is beneficial for generality and performance under an area constraint. Considering multi-granularity similarities across functions, Multi-Granularity DmDSE (MG-DmDSE) extends DSE through allocating finer granular and configurable ACCs and decomposing functions in the binding. MG-DmDSE produces a more general platform that benefited 87.5% of applications, while only 50% from GIDE. With a huge design space, DmDSE suffers from a long exploration time due to a large number of complex platform evaluations. Heuristics and machine learning methods are proposed to speed up DmDSE.This dissertation introduces Greedy Guided Mutation (GGM) to speed up the mutation in the GIDE algorithm, which calculates an ACC score according to current allocation to guide mutation. Alternatively, Rapid Domain Platform Performance Prediction (RDP^3) methods are introduced to replace a large number of the slow platform assessment in domain DSE, which avoids the complex application binding exploration. In the experiments, GGM reduces 84.8% of exploration time with a 0.23% loss of the final OpenVX domain platform's performance. RDP^3, using a machine learning method, yields an even more significant speedup, saving 90.8% of exploration time with only 0.0003% performance loss. DmDSE is a milestone to broaden DSE scope from individual applications to the domain level. It tremendously pushes the domain platform design from an experience-guided, manual effort into an automated process.--Author's abstract

This paper describes a novel and fast placement algorithm for FPGA design space (e.g., area, power or reliability) exploration. The proposed algorithm generates the placement based on the topological similarity between two configurations (netlists) in the design space. Thus, it utilizes the sharing of reusable information during the design space exploration and avoids the time-consuming placement computation like VPR. Tested on logic-level and algorithm-level design space exploration cases, our similarity-based placement accurately depicts the “shape” of a design space and pinpoints the designs which are of most interest to IC designers. Moreover, a turbo version of circuit similarity-based placement performs an average of 30x (up to 100x) faster than VPR's while still achieving comparable placement results.

Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using HPC architectures is very sensitive to the HPC parameters. Therefore it is very important to explore the HPC design space and carefully choose the HPC parameters that result in minimum energy consumption for the application. However, since in HPC architectures, the compiler has a significant impact on the energy consumption of the memory subsystem, it is extremely important to include compiler while deciding the HPC design parameters. While there has been no previous approaches to HPC design exploration, existing cache design space exploration methodologies do not include the compiler effects during DSE. In this paper, we present a Compiler-in- the-Loop (CIL) Design Space Exploration (DSE) methodology to explore and decide the HPC design parameters. Our experimental results on HP iPAQ h4300-like memory subsystem running benchmarks from the MiBench suite demonstrate that CIL DSE can discover HPC configurations with up to 80% lesser energy consumption than the HPC configuration in the iPAQ. In contrast, tradition simulation-only exploration can discover HPC design parameters that result in only 57% memory subsystem energy reduction. Finally our hybrid CIL DSE heuristic saves 67% of the exploration time as compared to the exhaustive exploration, while providing maximum possible energy savings on our set of benchmarks.

Exploration with a generative formalism must necessarily account for the nature of interaction between humans and the design space explorer. Established accounts of design interaction are made complicated by two propositions in Woodbury and Burrow's Keynote on design space exploration. First, the emphasis on the primacy of the design space as an ordered collection of partial designs (version, alternatives, extensions). Few studies exist in the design interaction literature on working with multiple threads simultaneously. Second, the need to situate, aid, and amplify human design intentions using computational tools. Although specific research and practice tools on amplification (sketching, generation, variation) have had success, there is a lack of generic, flexible, interoperable, and extensible representation to support amplification. This paper addresses the above, working with design threads and computer-assisted design amplification through a theoretical model of dialogue based on Grice's model of rational conversation. Using the concept of mixed initiative, the paper presents a visual notation for representing dialogue between designer and design space formalism through abstract examples of exploration tasks and dialogue integration.

Dataflow languages are widely used for programming real-time embedded systems. They offer high level abstraction above hardware, and are amenable to program analysis and optimisation. This paper addresses the challenge of verifying parallel program transformations in the context of dynamic dataflow models, where the scheduling behaviour and the amount of data each actor computes may depend on values only known at runtime. We present a Linear Temporal Logic (LTL) model checking approach to verify a dataflow program transformation, using three LTL properties to identify cyclostatic actors in dynamic dataflow programs. The workflow abstracts dataflow actor code to Fiacre specifications to search for counterexamples of the LTL properties using the Tina model checker. We also present a new refactoring tool for the Orcc dataflow programming environment, which applies the parallelising transformation to cyclostatic actors. Parallel refactoring using verified transformations speedily improves FPGA performance, e.g.15.4 × speedup with 16 actors.

Coarse-grained reconfigurable architectures (CGRAs) are gaining increasing attention as domain-specific accelerators due to their high flexibility and energy efficiency. These architectures offer a compelling solution for applications that require custom hardware performance while retaining a degree of programmability. However, the design space of CGRAs is inherently vast and complex, presenting significant challenges for architects to explore design choices efficiently and systematically. Existing design space exploration (DSE) methodologies for CGRAs are often time-demanding and struggle to deliver optimal solutions when confronted with high-dimensional and multi-objective design space. Therefore, we consider constructing a CGRA parameter tuning framework called MoDAF. MoDAF initializes the design space using the most representative and diverse samples. It adopts a divide-and-conquer approach, utilizing Monte Carlo Tree Search (MCTS) and space partitioning techniques to dynamically break down the complex design space into more manageable subspaces. A hybrid model handles local fluctuations within each subspace, while a dual sampling algorithm is designed to increase sampling efficiency. MoDAF also incorporates a fast evaluation model to estimate CGRA throughput and area, significantly speeding up the exploration process. Compared with previous approaches, experiments show that our proposed framework reduces the average distance from the reference set by 53.0% and the hypervolume deviation by 64.2%, while also cutting wall time by 57.5%.

The Internet of Things (IoT) makes use of ubiquitous internet connectivity to form a network of everyday physical objects for purposes of automation, remote data sensing and centralized management/control. IoT objects need to be embedded with processing capabilities to fulfill these services. The design of processing units for IoT objects is constrained by various stringent requirements, such as performance, power, thermal dissipation etc. In order to meet these diverse requirements, a multitude of processor design parameters need to be tuned accordingly. In this paper, we propose a temporally efficient design space exploration methodology which determines power and performance optimized microarchitecture configurations. We also discuss the possible combinations of these microarchitecture configurations to form an effective two-tiered heterogeneous processor for IoT applications. We evaluate our design space exploration methodology using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH2 benchmarks. The results show that our methodology determines microarchitecture configurations which are within 2.23–3.69 percent of the configurations obtained from fully exhaustive exploration while only exploring 3–5 percent of the design space. Our methodology achieves on average 24.16× speedup in design space exploration as compared to fully exhaustive exploration in finding power and performance optimized microarchitecture configurations for processors.

A regression-based design space exploration methodology is proposed that models the impacts of the memory hierarchy and the network-on-chip (NoC) on the overall chip multiprocessor (CMP) performance. Designers cannot explore all possible designs for a NoC without considering interactions with the rest of the uncore, in particular the cache configuration and memory hierarchy which determine the amount and pattern of the traffic on the NoC. The proposed regression model is able to capture the salient design points of the uncore for a comprehensive design space exploration by designing memory and NoC-specific regression models and leveraging recent advances in uncore simulation. To show the utility of our methodology, Uncore RPD, two case studies are presented: i) analyzing and refining regression models for an 8-core CMP and ii) performing a rapid design space exploration to find best performing designs of a NoC-based CMP given area-constraints for CMPs of up to 64 cores. Through these case studies, it is shown that i) simultaneous consideration of the memory and NoC parameters in the NoC design space exploration can refine uncore-based regression models, ii) sampling techniques must consider the dynamic design space of the uncore, and iii) overall, the proposed regression models reduce the amount of simulations required to characterize the NoC design space by up to four orders of magnitude.

Due to the large number of optimizations provided in modern compilers and to compiler optimization specific opportunities, a Design Space Exploration (DSE) is necessary to search for the best sequence of compiler optimizations for a given code fragment (e.g., function). As this exploration is a complex and time consuming task, in this paper we present DSE strategies to select optimization sequences to both improve the performance of each function and reduce the exploration time. The DSE is based on a clustering approach which groups functions with similarities and then explore the reduced search space provided by the optimizations previously suggested for the functions in each group. The identification of similarities between functions uses a data mining method which is applied to a symbolic code representation of the source code. The DSE process uses the reduced set identified by clustering in two ways: as the design space or as the initial configuration. In both ways, the adoption of a pre-selection based on clustering allows the use of simple and fast DSE algorithms. Our experiments for evaluating the effectiveness of the proposed approach address the exploration of compiler optimization sequences considering 49 compilation passes and targeting a Xilinx MicroBlaze processor, and were performed aiming performance improvements for 41 functions. Experimental results reveal that the use of our new clustering-based DSE approach achieved a significant reduction on the total exploration time of the search space (18x over a Genetic Algorithm approach for DSE) at the same time that important performance speedups (43% over the baseline) were obtained by the optimized codes.

Recent years have brought significantly increased interest in integrating wireless communication capability within factory automation systems. Such integration motivates the study of interactions among the physical layout of factory workcells, wireless communication among workcells, and improving the overall factory system performance. In this paper, we develop methods for modeling and simulating these interactions, and implement these methods into the experimental study of complex design spaces for factory automation systems. The proposed methodology for modeling, simulation, and design space exploration can be used to gain insight into approaches for improving the configuration (e.g., physical layout or wireless protocol settings) of existing factory systems, and for understanding trade-offs in the design of new systems.

Universal design space exploration for building energy design

Design space exploration (DSE) has become a notoriously difficult problem due to the exponentially increasing size of design space of microprocessors and time-consuming simulations. To address this issue, machine learning techniques have been widely employed to build predictive models. However, most previous approaches randomly sample the training set leading to considerable simulation cost and low prediction accuracy. In this paper, we propose an efficient and precise DSE methodology by combining statistical sampling and Adaboost learning technique. The proposed method includes three phases. (1) Firstly, orthogonal design based feature selection is employed to prune design space. (2) Sencondly, an orthogonal array based training data sampling method is introduced to select the representative configurations for simulation. (3) Finally, a new active learning approach ActBoost is proposed to build predictive model. Evaluations demonstrate that the proposed framework is more efficient and precise than state-of-art DSE techniques.

Typical design flows supporting the software development for multiprocessor systems are based on a board support package and high-level programming interfaces. These software design flows fail to support critical design activities, such as design space exploration or software synthesis. One can observe, however, that design flows based on a formal model of computation can overcome these limitations. In this article, we analyze the major challenges in multiprocessor software development and present a taxonomy of software design flows based on this analysis. Afterwards, we focus on design flows based on the Kahn process network (KPN) model of computation and elaborate on corresponding design automation techniques. We argue that the productivity of software developers and the quality of designs could be considerably increased by making use of these techniques.

Design space explorers are computer programs that play on an exploration metaphor to support design. They assist designers in creating alternative designs by structuring the process of design creation in a space of alternatives. Subsidiary metaphors relevant to design space explorers are generation, navigation, and reuse. This paper introduces, in two sketches, typed feature structures as a formal system in which a design space explorer and its knowledge level might be implemented. First, informal and abstract properties of typed feature structures suffice to build a sketch of the behavior of a design space explorer. Second, using an example based on single-fronted cottages (a common Australian housing type), we outline the typed feature structure machinery most relevant to design space exploration.