Efficient design space exploration via statistical sampling and AdaBoost learning

The design space exploration (DSE) of fault-tolerant multiprocessor systems is very complex, as it contains three interacting NP-hard problems: 1) task hardening; 2) task mapping; and 3) task scheduling. In addition, replication-based task hardening can introduce new tasks, called replicas, into the system, enlarging the design space further. As a population-based global optimization algorithm, evolutionary algorithms (EAs) have been widely used to explore this huge design space over the last decade. However, as analyzed in this paper, the search space of previous works is highly redundant, resulting in poor efficiency and scalability. This paper proposes an efficient EA-based DSE method for the design of large-scale fault-tolerant multiprocessor systems. The main novelties of this paper include: 1) mapping exploration is explicitly separated, i.e., task mapping is optimized during the evolutionary search, while replica mapping is constructed heuristically according to the current co-synthesis state; 2) the design space of task hardening and task mapping are explored independently by a cooperative co-EA; and 3) as a complement to global search of EA, problem-specific local search operators are designed for both task hardening and task mapping, reducing the number of fitness evaluations required. Compared with the most relevant state-of-the-art method, the superiority of the proposed method is demonstrated using extensive experiments on a large set of benchmarks, e.g., 1.75×~2.50× better results can be obtained on the benchmarks of 300 tasks and 30 processors.

Industrial Cyber-Physical Systems (CPS) are com-plex heterogeneous and distributed computing systems, typically integrating and interconnecting a large number of subsystems and containing a substantial number of hardware and software components. Producers of these distributed Cyber-Physical Systems (dCPS) face serious challenges with respect to designing the next generations of these machines and require proper support in making (early) design decisions to avoid expensive and time consuming oversights. This calls for efficient and scalable system-level Design Space Exploration (DSE) methods for dCPS. In this position paper, we review the current state of the art in DSE, and argue that efficient and scalable DSE technology for dCPS is more or less non-existing and constitutes a largely unchartered research area. Moreover, we identify several re-search challenges that need to be addressed and discuss possible directions for targeting such DSE technolozy for dCPS.

As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.

Detection of emergent shapes in sketches requires extensive exploration of the design space. Automating this process with computational methods enables locating various alternatives sequentially or all at once simultaneously via high computational power. This not only helps efficient design space exploration but also provides a systematic way for keeping track of the design process. However, it is a challenge to define a generic computational method which optimizes the design space searches in time and space. The approaches that are based on optimization may suffer from time efficiency and local minima problems. These problems are substantially solved in this work by performing comprehensive parallel searches in the design space with a genetic algorithm. Advantage of this approach is that the local minima problem is reduced significantly without increasing the execution times.

Designing the next‐generation complex distributed cyber‐physical systems (dCPS) poses significant challenges for manufacturing companies, necessitating efficient design space exploration (DSE) techniques to evaluate potential design decisions and their impact on nonfunctional aspects of the systems, such as performance, reliability and energy consumption. This paper introduces CompDSE, a methodology designed to facilitate the DSE of complex dCPS, specifically focusing on the cyber components, that is, the computing subsystems within dCPS. CompDSE defines and utilises abstract models of the application workload, computing hardware platform and workload‐to‐platform mapping of dCPS, automatically derived from runtime trace data, and integrates them into a discrete event simulation environment to explore various design points. We demonstrate the effectiveness of our methodology through a case study on the ASML TWINSCAN lithography machine, a complex industrial dCPS. The results showcase potential performance enhancements achieved by optimising computing subsystems while considering physical constraints. Evaluating each design point takes under a minute, highlighting the CompDSE efficiency and scalability in tackling complex dCPS with large design spaces.

High level Synthesis (HLS) or Electronic System Level (ESL) synthesis requires scheduling algorithms that have strong capability to reach optimal/near-optimal solutions with significant rapidity and greater accuracy. A novel power efficient scheduling approach using ‘PI’ method has been presented in this thesis that reduces the final power consumption of the solution at the expenditure of minimal latency clock cycles. The proposed scheduling approach is based on ‘Priority indicator (PI)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Application of the proposed approach results in even distribution of allocated hardware functional units thereby yielding power efficient scheduling solutions. The two main novel and significant aspects of the thesis are: a) Introduction of ‘Intersect Matrix’ topology with its associated algorithm which is used to check for precedence violation during scheduling b) Introduction of PI method using Priority indicator metric that assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach has been done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q- metric)’. This Q-metric is a combination of latency and power consumption values for the solution found, which dictates the quality of the final solutions found in terms of cost for both the proposed and existing approaches. An average improvement of approximately 12 % in quality of final solution and average reduction of 59 % in runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.

This work introduces an FPGA-based emulation method for optical communications DSP, using host-controlled data injection via high-performance (HP) interfaces on a local platform. An Multi-Modulus Algorithm (MMA) equalizer implemented on the FPGA processes MATLAB/Python-generated signals with optical impairments, emulating channel distortions without physical fiber. The trade-offs between fixed-point and floating-point precision are analyzed, and Cust<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">om</sup> Processing Units (CuPUs) are employed for acceleration. While not reaching real fiber speeds, this approach enables efficient DSP validation and design space exploration on accessible hardware.

Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and/or complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on an a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions—within the specific problem that is being optimized—have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves ε-dominance improvements of up to 95%.

ERDSE: efficient reinforcement learning based design space exploration method for CNN accelerator on resource limited platform

This paper describes a novel and fast placement algorithm for FPGA design space (e.g., area, power or reliability) exploration. The proposed algorithm generates the placement based on the topological similarity between two configurations (netlists) in the design space. Thus, it utilizes the sharing of reusable information during the design space exploration and avoids the time-consuming placement computation like VPR. Tested on logic-level and algorithm-level design space exploration cases, our similarity-based placement accurately depicts the “shape” of a design space and pinpoints the designs which are of most interest to IC designers. Moreover, a turbo version of circuit similarity-based placement performs an average of 30x (up to 100x) faster than VPR's while still achieving comparable placement results.

Constant false alarm rate (CFAR) algorithms are widely used in radar signal processing for object detection in cluttered and noisy environments and their fast hardware implementation is required in many of the real time applications. For that purpose, a parametrizable and runtime reconfigurable generator of CFAR detectors, featuring fully streaming I/O data interface, is captured inside Chisel hardware design language. Generator provides up to seven different CFAR algorithms available to choose from in compile time and throughout runtime configurability. Besides the algorithm choice, a wide range of settings, such as I/O data type and bit-widths, reference and guard window sizes, linear or logarithmic processing modes, edge handling methods, as well as some implementation specific parameters, are provided, hence enabling quick and efficient design space exploration. Several generator instances are tested and verified on a commercially-available FPGA board in conjunction with off-the-shelf radar transceivers thus proving that instances from the proposed peak detector generator can be effectively used whenever low latency processing performance is mandatory.

The design of efficient multiprocessor systems on chip (MPSoC) is a daunting challenge. This challenge is driven by the increasing demand in achieving high performance, low power, and reconfigurable applications onto the same platform. As a consequence, there is an emerging need for fast, and efficient design space exploration, while providing abstract models for a wide range of applications, and types of processing units (PUs). Therefore, this paper proposes a framework for a fast MPSoC generation with joint task and core mapping with the objective of minimizing the average power consumption. The proposed framework considers the static, dynamic, reconfiguration and communication power components. A tool for high level MPSoC task and core mapping (MPMAP) is built based on the proposed framework. MPMAP provides a flexible XML interface that provides a high level description of the different PU architectures, and different applications scenarios. Additionally, the paper presents a case study of real-life applications that can be adopted in future heterogeneous wireless systems.

The scarcity of methods for generating innovation systematically, quickly and without mistakes is felt across the technology intensive industries. An emerging autonomous robot industry produce the most complex artefacts ever made and stands to benefit most from effective design methods. In previous work, we described a framework for demand compliant design based on the existence of a demand catalogue and a method specific design database. In this paper, we show how to apply the method to an efficient exploration of design space starting a small and ill defined set of demands. Both the demand catalogue and design data are generated iteratively during the design process. We illustrate this process with the design of a hearing module for robots.

The Internet of Things (IoT) makes use of ubiquitous internet connectivity to form a network of everyday physical objects for purposes of automation, remote data sensing and centralized management/control. IoT objects need to be embedded with processing capabilities to fulfill these services. The design of processing units for IoT objects is constrained by various stringent requirements, such as performance, power, thermal dissipation etc. In order to meet these diverse requirements, a multitude of processor design parameters need to be tuned accordingly. In this paper, we propose a temporally efficient design space exploration methodology which determines power and performance optimized microarchitecture configurations. We also discuss the possible combinations of these microarchitecture configurations to form an effective two-tiered heterogeneous processor for IoT applications. We evaluate our design space exploration methodology using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH2 benchmarks. The results show that our methodology determines microarchitecture configurations which are within 2.23–3.69 percent of the configurations obtained from fully exhaustive exploration while only exploring 3–5 percent of the design space. Our methodology achieves on average 24.16× speedup in design space exploration as compared to fully exhaustive exploration in finding power and performance optimized microarchitecture configurations for processors.

We propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. At the heart of our framework, named AMPLE (adaptive microarchitectural planning engine), are wire delay-driven microarchitectural floorplanning and adaptive parameter tuning schemes that address interconnect issues with high exploration efficiency and accuracy. Our framework significantly outperforms the commonly used brute-force and simulated annealing methods in terms of exploration time efficiency as well as the performance and area quality for a large design space.