Wire-driven Microarchitectural Design Space Exploration

Design space exploration (DSE) has become a notoriously difficult problem due to the exponentially increasing size of design space of microprocessors and time-consuming simulations. To address this issue, machine learning techniques have been widely employed to build predictive models. However, most previous approaches randomly sample the training set leading to considerable simulation cost and low prediction accuracy. In this paper, we propose an efficient and precise DSE methodology by combining statistical sampling and Adaboost learning technique. The proposed method includes three phases. (1) Firstly, orthogonal design based feature selection is employed to prune design space. (2) Sencondly, an orthogonal array based training data sampling method is introduced to select the representative configurations for simulation. (3) Finally, a new active learning approach ActBoost is proposed to build predictive model. Evaluations demonstrate that the proposed framework is more efficient and precise than state-of-art DSE techniques.

Detection of emergent shapes in sketches requires extensive exploration of the design space. Automating this process with computational methods enables locating various alternatives sequentially or all at once simultaneously via high computational power. This not only helps efficient design space exploration but also provides a systematic way for keeping track of the design process. However, it is a challenge to define a generic computational method which optimizes the design space searches in time and space. The approaches that are based on optimization may suffer from time efficiency and local minima problems. These problems are substantially solved in this work by performing comprehensive parallel searches in the design space with a genetic algorithm. Advantage of this approach is that the local minima problem is reduced significantly without increasing the execution times.

The design space exploration (DSE) of fault-tolerant multiprocessor systems is very complex, as it contains three interacting NP-hard problems: 1) task hardening; 2) task mapping; and 3) task scheduling. In addition, replication-based task hardening can introduce new tasks, called replicas, into the system, enlarging the design space further. As a population-based global optimization algorithm, evolutionary algorithms (EAs) have been widely used to explore this huge design space over the last decade. However, as analyzed in this paper, the search space of previous works is highly redundant, resulting in poor efficiency and scalability. This paper proposes an efficient EA-based DSE method for the design of large-scale fault-tolerant multiprocessor systems. The main novelties of this paper include: 1) mapping exploration is explicitly separated, i.e., task mapping is optimized during the evolutionary search, while replica mapping is constructed heuristically according to the current co-synthesis state; 2) the design space of task hardening and task mapping are explored independently by a cooperative co-EA; and 3) as a complement to global search of EA, problem-specific local search operators are designed for both task hardening and task mapping, reducing the number of fitness evaluations required. Compared with the most relevant state-of-the-art method, the superiority of the proposed method is demonstrated using extensive experiments on a large set of benchmarks, e.g., 1.75×~2.50× better results can be obtained on the benchmarks of 300 tasks and 30 processors.

Industrial Cyber-Physical Systems (CPS) are com-plex heterogeneous and distributed computing systems, typically integrating and interconnecting a large number of subsystems and containing a substantial number of hardware and software components. Producers of these distributed Cyber-Physical Systems (dCPS) face serious challenges with respect to designing the next generations of these machines and require proper support in making (early) design decisions to avoid expensive and time consuming oversights. This calls for efficient and scalable system-level Design Space Exploration (DSE) methods for dCPS. In this position paper, we review the current state of the art in DSE, and argue that efficient and scalable DSE technology for dCPS is more or less non-existing and constitutes a largely unchartered research area. Moreover, we identify several re-search challenges that need to be addressed and discuss possible directions for targeting such DSE technolozy for dCPS.

Noise control is essential in an enclosed machine room where the noise level has to comply with the occupational safety and health act. In order to overcome a pure tone noise with a high peak value that is harmful to human hearing, a traditional reactive muffler has been used. However, the traditional method for designing a reactive muffler has proven to be time-consuming and insufficient. In order to efficiently reduce the peak noise level, interest in shape optimization of a Helmholtz muffler is coming to the forefront. Helmholtz mufflers that deal with a pure tone have been adequately researched. However, the shape optimization of multi-chamber Helmholtz mufflers that deal with a broadband noise hybridized with multiple tones within a constrained space has been mostly ignored. Therefore, this study analyzes the sound transmission loss (STL) and the best optimized design for a hybrid Helmholtz muffler under a space- constrained situation. On the basis of the plane wave theory, the four-pole system matrix used to evaluate the acoustic performance of a multi-tone hybrid Helmholtz muffler is presented. Two numerical cases for eliminating one/two tone noises emitted from a machine room using six kinds of mufflers (muffler A~F) is also introduced. To find the best acoustical performance of a space-constrained muffler, a numerical assessment using a simulated annealing (SA) method is adopted. Before the SA operation can be carried out, the accuracy of the mathematical model has been checked using the experimental data. Eliminating a broadband noise hybridized with a pure tone (130 Hz) in Case I reveals that muffler C composed of a one- chamber Helmholtz Resonator and a one-chamber dissipative element has a noise reduction of 54.9 (dB). Moreover, as indicated in Case II, muffler F, a two-chamber Helmholtz Resonator and a one-chamber dissipative element, has a noise reduction of 69.7 (dB). Obviously, the peak values of the pure tones in Case I and Case II are efficiently reduced after the muffler is added. Consequently, a successful approach in eliminating a broadband noise hybridized with multiple tones using optimally shaped hybrid Helmholtz mufflers and a simulated annealing method within a constrained space is demonstrated.

High level Synthesis (HLS) or Electronic System Level (ESL) synthesis requires scheduling algorithms that have strong capability to reach optimal/near-optimal solutions with significant rapidity and greater accuracy. A novel power efficient scheduling approach using ‘PI’ method has been presented in this thesis that reduces the final power consumption of the solution at the expenditure of minimal latency clock cycles. The proposed scheduling approach is based on ‘Priority indicator (PI)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Application of the proposed approach results in even distribution of allocated hardware functional units thereby yielding power efficient scheduling solutions. The two main novel and significant aspects of the thesis are: a) Introduction of ‘Intersect Matrix’ topology with its associated algorithm which is used to check for precedence violation during scheduling b) Introduction of PI method using Priority indicator metric that assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach has been done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q- metric)’. This Q-metric is a combination of latency and power consumption values for the solution found, which dictates the quality of the final solutions found in terms of cost for both the proposed and existing approaches. An average improvement of approximately 12 % in quality of final solution and average reduction of 59 % in runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.

The quest to democratize the use of Field-Programmable Gate Arrays (FPGAs) has given High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors strongly supporting this VLSI design methodology to expand the FPGA user base. HLS takes as input an untimed behavioral description and generates efficient RTL (Verilog or VHDL). One major advantage of HLS is that it allows us to generate a variety of different micro-architectures from the same behavioral description by simply specifying different combination of synthesis options. In particular, commercial HLS tools make extensive use of synthesize directives in the form pragmas. This strength is also a weakness as it forces HLS users to fully understand how these synthesis options work and how they interact to efficiently set them to get a hardware implementation with the desired characteristics. Luckily, this process can be automated. Unfortunately, the search space grows supra-linearly with the number of synthesis options. To address this, this work proposes an automatic synthesis option tuner dedicated for FPGAs. We have explored a larger number of behavioral descriptions targeting ASICs and FPGAs and found out that due to the internal structure of the FPGA a large number of synthesis options combinations never lead to a Pareto-optimal design and, hence, the search space can be drastically reduced. Moreover, we make use of large database of DSE results that we have generated since we started working in this field to further accelerate the exploration process. For this, we use a technique based on perceptual hashing that allows our proposed explorer to recognize similar program structures in the new description to be explored and match them with structures in our database. This allows us to directly retrieve the pragma settings that lead to Pareto-optimal configurations. Experimental results show that the search space can be accelerated substantially while leading to finding most of the Pareto-optimal designs.

This work introduces an FPGA-based emulation method for optical communications DSP, using host-controlled data injection via high-performance (HP) interfaces on a local platform. An Multi-Modulus Algorithm (MMA) equalizer implemented on the FPGA processes MATLAB/Python-generated signals with optical impairments, emulating channel distortions without physical fiber. The trade-offs between fixed-point and floating-point precision are analyzed, and Cust<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">om</sup> Processing Units (CuPUs) are employed for acceleration. While not reaching real fiber speeds, this approach enables efficient DSP validation and design space exploration on accessible hardware.

Today's linear algebra and machine learning applications (ML) continue to grow in size and complexity, placing rapidly increasing demands on the underlying hardware and software systems. To address these issues, hardware designers have proposed using custom accelerators explicitly designed for these demanding workloads. However, realizing the full potential of custom accelerators requires effective hardware/software (HW/SW) co-design strategies that enable seamless integration and optimization across both domains, which is currently a major challenge in accelerator development. This thesis presents an integrated solution to facilitate HW/SW accelerator design. We also address issues in accelerator deployment, enabling rapid prototyping, integrated benchmarking, and comprehensive performance analysis of custom accelerators. In this thesis, we demonstrate the value of a lightweight system modeling library integrated into the build/execution environment of a production ML runtime engine, leveraging TensorFlow Lite for deployment. We explore custom accelerators performance by analyzing the trade-offs between various design choices, including parameter settings and accelerator configurations, from small to large scale, to identify the most effective combinations for specific workloads. Secondly, we employ the Multi-Level Intermediate Representation (MLIR) compiler framework to automatically partition host code from accelerator code, pre-optimizing the latter for improved high-level synthesis (HLS) designs and high-quality accelerated kernels. Lastly, we present compiler extensions to automate the generation and optimization of communication between the host CPU and AXI-based accelerators. We present novel solutions that enable more efficient and effective design space exploration, optimization, and deployment of custom accelerators. The utility of these approaches is demonstrated through experiments with specific accelerator designs and key linear algebra and ML workloads. Most importantly, these solutions empower high-level language users, such as domain scientists, to participate in the design of new accelerator features.--Author's abstract

Calculating the spatial structures of ion crystals is important in ion-trapped quantum computation. Here we demonstrate that the simulated annealing method is a powerful tool to evaluate the structures of ion crystals. By calculating equilibrium positions of 10 ions under harmonic potential and those of 120 ions under anharmonic potential, both with the standard procedure and simulated annealing method, we find that the standard procedure to evaluate spatial structures is complicated and may be inefficient in some cases, and that the simulated annealing method is more favorable.

PurposeAccurate presentation of the rock microstructure is critical to the grain-scale analysis of rock deformation and failure in numerical modelling. 3D granite microstructure modelling has only been used in limited studies with the mineral pattern often remaining poorly constructed. In this study, the authors developed a new approach for generating 2D and 3D granite microstructure models from a 2D image by combining a heterogeneous material reconstruction method (simulated annealing method) with Voronoi tessellation.Design/methodology/approachMore specifically, the stochastic information in the 2D image is first extracted using the two-point correlation function (TPCF). Then an initial 2D or 3D Voronoi diagram with a random distribution of the minerals is generated and optimised using a simulated annealing method until the corresponding TPCF is consistent with that in the 2D image. The generated microstructure model accurately inherits the stochastic information (e.g. volume fraction and mineral pattern) from the 2D image. Lastly, the authors compared the topological characteristics and mechanical properties of the 2D and 3D reconstructed microstructure models with the model obtained by direct mapping from the 2D image of a real rock sample.FindingsThe good agreements between the mapped and reconstructed models indicate the accuracy of the reconstructed microstructure models on topological characteristics and mechanical properties.Originality/valueThe newly developed reconstruction method successfully transfers the mineral pattern from a granite sample into the 2D and 3D Voronoi-based microstructure models ready for use in grain-scale modelling.

An LSI module placement algorithm which uses neural networks is presented. A formula which determines the weighting factors of the constraint and objective function in the energy so that they converge to a vertex, a point on the edge, or an interior point of the hypercube is derived. In a comparison with simulated annealing and min-cut methods, the proposed method was as good as the min-cut method but not as good as the simulated annealing method

Although there are several well -known methods such as RCWA, FMM, for analyzing the diffraction properties of gratings, design of these optical elements with specified spectral properties is commonly a challenging problem. It is relatively not easy for the researchers to design narrow line-with diffraction filters based on guided mode resonance phenomenon with common diffraction algorithm. Simulated Annealing (SA) method is evolutionary, robust technique that has been widely utilized to design optical diffraction components. This method is inspired by the physical process of heating and controlled cooling of metal material to increase the size of its crystals and reduce their defects. The most distinctive features of this method lie in its powerful ability of convergence towards the global minimum in a reasonable computation time and the independence of the initial parameter values. In this paper, first, the physical basis of SA and its mathematical realization are introduced. Then, a Guided-Mode Resonant Grating (GMRG) filters with single layer is designed by using SA algorithm. The central wavelength of GMRG filter is locked at 532nm and its line-width is fixed at 1nm. The plane wave light radiates the grating from air cover with normal incidence. The optimized parameters are refractive indices and thicknesses of high and low material of grating, other parameters are grating period and fill factor of the grating. It is shown from our calculation that an excellent reflection spectrum with narrow line-width, high peak and low sideband can be obtained after optimizing the grating parameters. Next, a double layered GMRG filter with line-width of 4nm, which is relatively easy fabrication in experiment, is designed at central wavelength of 1064nm. The optimized parameters are grating period, groove depth, refractive index of waveguide layer and fill factor respectively. The grating substrate and waveguide layer are Sio2 and Hfo2 respectively, the grating structure is directly etched on the waveguide layer. The above grating values should be included in reasonable ranges in consideration of grating fabrication in our experiment condition. It is demonstrated from the calculations with the parameters obtained from SA optimization algorithm that the peak diffraction efficiency is more than 99% at central wavelength 1064nm and the sideband reflection is depressed at the level bellow 5% in a large wavelength range. Moreover, the parameters of a triple layer GMRG filter structure are also provided with this powerful method. Meanwhile, the results found by SA method are compared with RCWA theory.

An efficient scheduling algorithm using the Simulated Annealing (SA) method is proposed. In an actual large scheduling problem, the number of schedules searched within a reasonable time is restricted, because calculation of the starting times of jobs requires a long computation time when the problem has various types of constraints. In the proposed algorithm, two types of improvements are proposed to reduce the computation time of a scheduling algorithm: One is to reject, at an early stage of the starting time calculation, those schedules that have little possibility of being accepted in the simulated annealing method. The other is to reject unpromising schedules stochastically using the data related to the production sequence of jobs—not after the calculation of the starting times of jobs but at the step of generating a new production sequence of jobs. Thus, compared with the algorithm which selects a new production sequence randomly, better schedules can be derived in shorter computation time. The developed algorithm has been applied to a practical scheduling problem at a resin production plant, and it has become clear that this algorithm can generate significantly better schedules with a much shorter computation time.

&lt;span&gt;The increasing demand of electricity and number of distributed generations connected to power system greatly influence the level of power service reliability. This paper aims at improving the reliability in an electric power distribution system by optimizing the number and location of sectionalizers using the Ant Colony Optimization (ACO) and Simulated Annealing (SA) methods. Comparison of these two methods has been based on the reliability indices commonly used in distribution system: SAIFI, SAIDI, and CAIDI. A case study has been taken and simulated at a feeder of Pujon, a place in East Java province of Indonesia, to which some distributed generators were connected. Using the existing reliability indices condition as base reference, the addition of two distributed plants, which were micro hydro and wind turbine plants, has proven to lower the indices as much as 0.78% for SAIFI, 0.79% for SAIDI, and 2.32% for CAIDI. The optimal relocation of the existing 16 sectionalizers in the network proved to decrease further the reliability indices as much as 43.96% for SAIFI, 45.52% for SAIDI, and 2.8% for CAIDI, which means bringing to much better reliability condition. The implementation of the SA method on the considered data in general resulted in better reliability indices than using the ACO method.&lt;/span&gt;