A high-density dual-port memory cell operation and array architecture for ULSI DRAMs

Disturb failures are considered the most predominant failure mode in flash memories. Disturb faults are highly dependant on the core memory cell structure, manufacturing technology, and array organization and operation. In this paper, we develop appropriate fault primitives for all possible disturb faults in flash memories. Further, we analyze the origins of such disturbs and propose a method that uses cell structure and array organization information to identify the relevant disturbs to create reduced list of faults. As an example, the method was used to create a minimized faults list for NOR and NAND flash memory arrays. Moreover, we show how the reduced fault list developed can be used to devise more efficient test algorithms.

The article is devoted to increasing the coefficient of technical readiness of memory chips. The architecture of built-in self-test and repair is proposed, what allows changing a bit data of the primary array of memory cells, in which the failure is occurred, on the data coming from the outputs of an array of backup memory cells. The proposed hardware and software provide automatic reconfiguration of the data upon failure of chip.

This paper describes the yield enhancement effects of a boosted dual word-line (BDWL) scheme for the first Al wiring in high density DRAMs, with a defect density model and a yield model used for comparison with that of the commonly used word-shunt (WS) scheme. Additionally, the yield of first Al wiring with a step height between memory cell array and peripheral circuit regions is also estimated. The yield estimation demonstrated that the yield enhancement effect of the wide first Al wiring for the BDWL scheme was comparable with or surpassed that of the redundancy for the WS scheme yield, when the first Al wiring pitch over the memory cell array or a BDWL scheme was over 4 times wider than that of the WS scheme. The yield estimation with step height indicated that the first Al wiring yield of the BDWL scheme with the step height exceeded that of the WS scheme with the step height of zero, even if using some global planarization technology.

An array of substrate-plate trench-capacitor dynamic random access memory (DRAM) cells is used for quantification of parasitic leakage mechanisms, silicon defects, and device parametrics. Parasitic devices aid process characterization, parametric cross-correlations, and technology/device design-point evaluation. Used in conjunction with a functional monitor, the trench leakage monitor, is found to be a valuable semiconductor process-development vehicle to achieve functionality and cell-retention yield for a 4-Mb DRAM CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance modeling and optimization for on-chip interconnects in DRAM arrays are presented at various technology generations. Multiple interconnect design schemes and novel interconnect technology options are investigated to minimize the overall delay and energy-delay product.

Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T- 2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic “1” and 0 V as a logic “0”. Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of 6×10-5 mW per cell and dynamic power dissipation of 1.8×10-7 mW/MHz per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.

The speed of modern digital systems is severely limited by memory latency (the ``Memory Wall'' problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic--In--Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK $\SI{45}{\nano\meter}$ CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in--memory operations result to be very efficient: a 55.26\% reduction in the energy--delay product is measured for the AND operation with respect to the SRAM read one; therefore, the LiM approach represents a very promising solution for low--density and high--performance memories.

An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F/sup 2/ memory cell, where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The first frame-transfer CMOS active pixel sensor (APS) is reported. The sensor architecture integrates an array of active pixels with an array of passive memory cells. Charge integration amplifer-based readout of the memory cells permits binning of pixels for variable resolution imaging. A 32/spl times/32 element prototype sensor with 24-/spl mu/m pixel pitch was fabricated in 1.2-/spl mu/m CMOS and demonstrated.

The use of coarse-grain reconfigurable architectures (CGRA) is a suitable alternative for hardware acceleration in many application areas, including digital holographic imaging. In this paper, we propose a CGRA-based system with an array of processing and memory cells, which communicate using a local and a global communication network, and a stream memory controller to manage data transfers to external memory. We present our SystemC-based exploration environment (SCENIC) and methodology used to construct and evaluate systems containing reconfigurable architectures. A case study illustrates the advantages with rapid system level exploration to find and solve bottlenecks in complex designs prior to RTL description.

This paper proposes a new hicrarchical sensing scheme (HSS) that realizes stability in READ/WRITE operation for a small SRAM memory cell. By adopting the HSS, highdensity and low-voltage operation SRAMs with a small diesize, which is suitable for mobile multi-media devices, can be realized. The HSS makes best use of Cb/Cs relation in the circuit design. The simulation show that the HSS SRAM functions satisfactory with a cell ratio of 1.5 (< 50% of conventional) at Vcc = 3V and 2.5 at Vcc = 1.8V. 1, Introduct ion As portable machinery such as handy terminals and lap-top personal computers increase their market share, the demand for high-density and low-voltage operation memories has increased. A large cell ratio such as 3 to 4 is necessary for stablc memory cell operation. Therefore, 3 to 4 times large transistor has to be integrated in a memory cell. Because of this large cell ratio requirement, it is difficult to realize a high-density SRAM. For a low-voltage operation, the six-transistor full-CMOS cell [l] or the boosted word line technique [21 are used. These technologies, however, require a larger die size or elaborated circuits and fabrication processes. This paper proposes a hierarchical sensing scheme (HSS) that make both high-density and low-voltage operation possible for SRAMs with smaller memory cells. 2. Hierarchical Sensine Scheme (HSS)

Area-Delay-Energy aware SRAM memory cell and M × N parallel read/write memory array design for quantum dot cellular automata

A 16-kbit nonvolatile charge addressed memory (NOVCAM) is described. A unique cell design allows a high-density memory array layout without reduced line widths or spacings. A cell size of 0.5 square mils is produced by a seven mask process with 6-/spl mu/m polysilicon gates, 10-/spl mu/m aluminum gates, and 10-/spl mu/m minimum spacing on all mask levels. Charge addressed write and read operations are implemented with a very simple interface between the memory array and a two-phase dynamic shift register. The memory is organized as 256 columns by 64 rows. Two 64-bit shift registers provide data access to the memory array via a 2:1 column decoder. With single polysilicon processing the memory array is 50/spl times/161 mils; the 16-kbit chip is 131/spl times/200 mils.

High-density memory arrays require selector devices, which enable selection of a specific memory cell within a memory array by suppressing leakage current through unselected cells. Such selector devices must have highly nonlinear current-voltage characteristics and excellent endurance; thus selectors based on a tunneling mechanism present advantages over those based on the physical motion of atoms or ions. Here, we use two-dimensional (2D) materials to build an ultrathin (three-monolayer-thick) tunneling-based memory selector. Using a sandwich of h-BN, MoS2, and h-BN monolayers leads to an "H-shaped" energy barrier in the middle of the heterojunction, which nonlinearly modulates the tunneling current when the external voltage is varied. We experimentally demonstrate that tuning the MoS2 Fermi level can improve the device nonlinearity from 10 to 25. These results provide a fundamental understanding of the tunneling process through atomically thin 2D heterojunctions and lay the foundation for developing high endurance selectors with 2D heterojunctions, potentially enabling high-density non-volatile memory systems.

A single-chip architecture for a 10/sup 6/-synapse neural network is proposed. It operates on a 1.5-V dry cell so that it can be used in portable equipment. An on-chip DRAM cell array stores 10/sup 6/ 8-b synapse weights digitally. These are readily programmable and refreshable. A pitch-matched interconnection and a combinational unit circuit used for summing product provide a tight layout by eliminating bus lines between the memory cell array and the product-summation circuit. A dynamic data transfer circuit directly coupled to the DRAM cell array, together with 1.5-V operation of the entire chip, reduces the power dissipation to 75 mW. The 256 parallel circuits for summing product provide a processing speed of 1.37 gigaconnections/s. The memory and the processing circuits can be integrated on a 15.4-mm*18.6-mm chip by using a 0.5- mu m CMOS design rule. >