Fault Collapsing for Flash Memory Disturb Faults

As a synaptic device, TFT-type NOR flash memory cell shows reasonable weight levels (50 levels for long-term potentiation (LTP) and 150 levels for long-term depression (LTD)) and large max/min ratio (═50) for synapse weight. Based on the measurement results of the synapse cell, supervised learning process is simulated using software MATLAB. A new pulse scheme is designed for mimicking spike-rate-dependent plasticity (SRDP) algorithm. Through learning and inferencing phase, our (784 × 100) network achieved 74.08% accuracy on the MNIST benchmark. A new method for adapting the threshold voltage of output neurons for firing is also proposed. This additional adjustment helps to eliminate the exclusive or dormant output neurons by setting the threshold voltage to an appropriate value proportional to the average weight of synapses connected to each neuron. As a result, accuracy increases to 82.54% in the (784 × 100) network and to 84.14% in the (784 × 200) network. Moreover, threshold adjustment helped the network to classify completely overlapped patterns in succession.

In this work, we present the first implementation of spike-timing-dependent plasticity (STDP) and unsupervised learning in a mainstream NOR Flash memory array based on floating-gate cells. A simple yet effective word-line and bit-line pulse scheme is proposed to make a common-ground double-polysilicon NOR array in 40 nm embedded technology work as an artificial synaptic array in a spiking neural network learning according to the STDP rule, with no change required either to the array or to the cell design. With this scheme, long-term potentiation and long-term depression of the synaptic weights are achieved, respectively, by hot-hole injection and channel hot-electron injection at the drain side of the cells. Unsupervised learning is experimentally demonstrated in the array, paving the way for the development of large-scale and high-density neuromorphic systems based on mainstream nonvolatile memory technologies.

This paper proposes a new structure with counter lightly doped drain (C-LDD) implantation for Multi-level cell (MLC) NOR flash memory application, aimed at reducing drain disturb. The manufacturing of C-LDD cell is fully compatible with standard floating gate flash process and no extra mask is required. Experimental results show that, by introducing C-LDD structure, the drain disturb can be successfully inhibited compared with conventional flash cell due to the optimization of drain junction doping profile. Endurance reliability is also improved when C-LDD is adopted. In addition, experiments reveal that no program degradation is observed when applying C-LDD implantation. These advantages have shown that C-LDD structure is a low cost and effective way to obtain high reliability in NOR flash memory.

The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm/sup 2/ was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-/spl mu/m CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.

The framework of this article lies in the dynamic management of the reliability in NOR embedded Flash memories (eFlash). The main objective is to build a new reliability management scheme and to predict its efficiency to improve the eFlash reliability using error correction code and redundancy. The originality of the proposed approach relies on the use of a dedicated error correcting code well suited to NOR flash memories operational conditions. This code, named hierarchical code, improves the correction capabilities with a minimal impact on performance and area. The proposed solution furthermore enables selecting different built-in self strategies allowing to tune reliability strategies to the targeted application domain.

We have designed, fabricated, and tested a prototype mixed-signal, 28×28-binary-input, 10-ouput, 3-layer neuromorphic network based on embedded nonvolatile floating-gate cell arrays redesigned from a commercial 180-nm NOR flash memory. Each array performs a very fast and energy-efficient analog vector-by-matrix multiplication, which is the bottleneck for signal propagation in neuromorphic networks. All functional components of the prototype circuit, including 2 synaptic arrays with 101,780 floating-gate synaptic cells, 74 analog neurons, and the peripheral circuitry for weight adjustment and I/O operations, have a total area below 1 mm2. Its testing on the MNIST benchmark set has shown a classification fidelity of 94.65%, close to the 96.2% obtained in simulation. The classification of one pattern takes 103× better than those of the 28-nm IBM TrueNorth digital chip for the same task at a similar fidelity. Estimates show that this performance may be further improved using a better neuron design and a more advanced memory technology, leading to a >102x advantage in speed and a >104x advantage in energy efficiency over the state-of-the-art purely digital circuits for classification of large, complex patterns. Experimental results for the chip-to-chip statistics, long-term drift, and temperature sensitivity show no evident showstoppers on the way toward practical deep neuromorphic networks with unprecedented performance.

This session will discuss papers related to nanoscale poly floating-gate and charge trap non-volatile memories. The first two papers are on poly-floating gate technologies, the next three are on charge-trap flash memories and the last two are on 3-D NAND flash memories. In the first paper, Toshiba Corporation reports a floating-gate multi-level NAND flash memory technology scalable to 30nm and beyond technology nodes. In the second paper, Qimonda and the Technical University of Munich present a stochastic model of the program operation in scaled NAND flash memories for investigating the interactions between the memory cell and the memory system. Charge-Trap Flash: The next paper by Numonyx and Politecnico di Milano investigates the Random Telegraph Noise scaling trend for both NAND and NOR flash memories. The fourth paper by Toshiba Corporation presents the scalability of a bulk planar SONOS flash memory with double-tunnel junctions down to 10nm gate length. The next paper by National Tsing Hua and Chiao-Tung University reports a new charge-trap engineered non-volatile memory device with very good memory window and high-temperature data retention. 3-D SONOS Flash: In the fifth paper, Schiltron Corporation presents a novel 3-D stackable high-density flash technology, which combines the smallest TFTs to date in series with strings up to 64 cells in a unique architecture to effectively remove pass disturbs. The last paper by Toshiba Corporation, demonstrates a four NAND string 3-D bit cost scalable flash memory with improved program, erase and disturb operation.

A NOR Flash memory fully functional at 1 V is demonstrated, based on an inductor built directly into the package. A ferromagnetic nucleus is wound by means of the bonding wires and the first package substrate metal layer. The magnetic field does not affect the system since it is strictly confined into the toroidal nucleus. The whole system is enclosed into a standard BGA package 8×14×1.4 mm with 88 balls.

By utilizing the fringing electric field from the control gate of cells in NAND flash memory string, the source/drain in the cells could be removed, which improves cell scalability and gives very positive effects. In this scheme, cells with underlapped S/D or localized buried oxide in the space shown more reasonable read current characteristics. For NOR flash memory, cells with recess channel structure have studied. We demonstrated successful operation of 4-bit/cell using the recess structure and found no interference in a cell and adjacent cells. Finally, we compared measured RTN in FinFET SONOS and saddle SONOS devices. The current fluctuation of the FinFET devices is higher by ~3 times than that in the saddle devices. We expect that our approach is very promising for future high density and high performance flash memory technology.

Flash memories are nonvolatile memories, i.e., they are able to retain information even if the power supply is switched off. These memories are characterized by the fact that the erase operation (the writing of logic “1”) has to be performed at the same time on a group of cells called a sector or block; on the other hand, the program operation (the writing of logic “0”) is a selective operation during which a single cell is programmed. The fact that the erase can be executed only on an entire sector allows one to design the matrix in a compact shape and therefore in a very competitive size, from an economic point of view. Depending on how the cells are organized in the matrix, it is possible to distinguish between NAND Flash memories and NOR Flash memories. The main electric characteristics are reported below.KeywordsThreshold VoltageFlash MemoryNonvolatile MemoryProgram OperationRead OperationThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

We study the effects of exposure to accelerated neutron beams of Floating Gate (FG) Flash memories with NOR architecture. Error rates as well as threshold voltage shifts are examined and mechanisms are discussed. A comparison with NAND Flash memories, with both multi-level and single-level cell architecture, is performed. In addition to prompt effects, retention of irradiated cells is analyzed for several months after irradiation. Thanks to tail distributions, we can assess possible rare events.

This chapter focuses on advanced experiments and improvements in the security features of the SATA solid-state drives. In modern computer applications, the quantity of data is growing day by day, and accordingly, the size of storage media is also increasing rapidly. Flash memories are used in most storage devices, one of which is a Solid State drive. Solid-state drives, or SSDs, are non-volatile data storage devices that store data in NAND or NOR flash memories, providing features similar to traditional hard disk drives (HDD). This chapter provides a comparative study of Solid-state drives over Hard-disk drives. Further, a technique is designed and implemented to enhance SATA Solid-state drives security features in terms of user authentication, access control, and media recovery from the ATA security feature set.

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed. >

A few commercial NOR Flash memories are investigated in total ionizing dose (TID) experiment, one in dynamic mode, one in static mode, one in hot back-up and one in cold back-up. The experiment shows that the dynamic bias mode in which erasure and program are executed frequently is the worst bias mode and charge pump is most critical to TID effects in dynamic bias. The failure mechanism of charge pump is explained with emphasis, i.e. the threshold voltage drift plays a more critical role in charge pump's performance when the accumulated radiation dose is low while the radiation induced leakage current effects more obviously as the accumulated dose goes high.

A new concept for improving efficiency of a charge pump system is presented. The concept is based on a set of elementary charge pumps connected in parallel in addition to the detection of the number of memory cells to be programmed at the same time. The proposed solution is able to supply current to a memory cell, while operating with maximum efficiency by activating one, two or more charge pumps. The proposed system is implemented using a 55 nm UMC High Voltage CMOS technology with a power supply of 1.2V. In the worst case where only one cell is to be programmed, simulation results show an improvement of power efficiency by a factor 2. The area penalty of the proposed system is only 3.8%.