A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding

With the recent advancement of nanometer process technologies and the growing interest in scaled supply voltage operation, we are facing increasing challenges to robust design due to process, voltage, and temperature (PVT) variation. One promising direction is to consider asynchronous pipelines, which eliminate the need for fixed-rate clock distribution. However, while conventional single-rail bundled-data asynchronous pipeline styles can mitigate global and spatial variations by closely placing the delay elements to their corresponding pipeline stages, random variations are currently not effectively handled. In particular, timing margins must be added to the matched delay elements in each stage, resulting in reduced performance and increased leakage power consumption. Building upon a well-known asynchronous pipeline, MOUSETRAP, this paper proposes a scheme to mitigate the impact of random PVT variations over a range of supply voltages. We introduce the notion of soft latching for asynchronous pipelines: allowing data registers to latch their incoming data during a wider sampling window. As a result, the pipeline operates correctly even with random PVT variation-induced delay mismatch between a bundled delay and its corresponding pipeline stage. However, the inclusion of soft latching can exacerbate hold time violations, these are mitigated through a novel protocol modification. The new asynchronous soft-latching scheme shows significant energy-efficiency and performance improvement over the conventional margining approach, it also robustly operates down to 0.3V even in the presence of random process variations.

Pipeline requires both low latency and high throughput. Synchronous pipeline achieves a near optimized throughput but suffers from the worst-case computation delay. Meanwhile, asynchronous pipeline keeps an optimized computation delay but suffers from the low throughput. In this paper, we present dual control path (DCP), a new structure of four-phase handshake asynchronous control path, to improve the throughput of asynchronous pipeline. We leverage the existing fully decoupled four-phase handshake elements and asymmetric delay elements to found DCP. Experimental results show the asynchronous pipeline with DCP could achieve high throughput as well as low computation delay, only with tiny area overhead.

In high level synthesis, resource sharing may result in a circuit containing false loops that pose great difficulty in timing validation during design sign-off phase. It is hence desirable to avoid generating any false loops in a synthesized circuit. Previous work considered mainly data path sharing for false loop elimination. However, for a complete circuit with both data path and control path, false loops can be created due to control logic sharing, even though the loops caused by data path sharing have all been removed. In this paper we present a novel approach to detect and eliminate the false loops caused by control logic sharing. An effective filter is devised to reduce the computation complexity of false loop detection, which is based on checking the level numbers that are propagated from data path operators to inputs/outputs of the control path. Only the input/output pairs of the control path identified by the filter are further investigated by traversing into the data path for false loop detection. A removal algorithm is then applied to eliminate the detected false loops, followed by logic minimization to further optimize the circuit. Experimental results show that for nine example circuits we tested, the final designs after false loop removal and logic minimization give only slightly larger area than the original ones that contain false loops.

This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.

This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Control and monitoring of the DØ detector

The authors describe design and experimental results of a Josephson data processor, designed to demonstrate the possibility of a Josephson computer system with a gigahertz clock. It is a stored-program-type full processor including both a data path and a control path, and is constructed from 2066 three-junction interferometer devices on a 5*5-mm/sup 2/ die. An eight-instruction set to enable the basic operations of digital signal processing is implemented. The design rule is 2.5 mu m. The junctions were fabricated using an Nb-AlO/sub x/-Nb process. A new latchup-free DC flip-flop is used in the registers. A DC output buffer eliminates crosstalk from the AC power to the output signals. A stacked AC supply reduces the required AC current amplitude by one quarter. The power dissipation is 25 mW and minimum gate delay is 9 ps. Operation could be confirmed up to a 1.02-GHz clock frequency. >

The authors describe design and experimental results of a Josephson data processor, designed to demonstrate the possibility of a Josephson computer system with a gigahertz clock. It is a stored-program-type full processor including both a data path and a control path, and is constructed from 2066 three-junction interferometer devices on a 5*5-mm/sup 2/ die. An eight-instruction set to enable the basic operations of digital signal processing is implemented. The design rule is 2.5 mu m. The junctions were fabricated using an Nb-AlO/sub x/-Nb process. A new latchup-free DC flip-flop is used in the registers. A DC output buffer eliminates crosstalk from the AC power to the output signals. A stacked AC supply reduces the required AC current amplitude by one quarter. The power dissipation is 25 mW and minimum gate delay is 9 ps. Operation could be confirmed up to a 1.02-GHz clock frequency. >

Evaluating the added value of multi-input atmospheric transport ensemble modeling for applications of the Comprehensive Nuclear Test-Ban Treaty organization (CTBTO)

In this paper, we present design for testability (DFT) and hierarchical test generation techniques for facilitating the testing of application-specific programmable processors (ASPPs) and application-specific instruction processors (ASIPs). The method utilizes the register-transfer level (RTL) circuit description of an ASPP or ASIP to come up with a set of test microcode patterns which can be written into the instruction read-only memory (ROM) of the processor. These lines of microcode dictate a new control/data flow in the circuit and can be used to test modules which are not easily testable. The new control/data flow is used to justify precomputed test sets of a module from the system primary inputs to the module inputs and propagate output responses from the module output to the system primary outputs. The testability analysis, which is based on the relevant control/data flow extracted from the RTL circuit, is symbolic. Thus, it is independent of the bit-width of the data path and is extremely fast. The test microcode patterns are a by-product of this analysis. If the derived test microcode cannot test all untested modules in the circuit, then test multiplexers are added (usually to the off-critical paths of the data path) to test these modules. This is done to guarantee the testability of all modules in the circuit. If the control microcode memory of the processor is erasable, then the test microcode lines can be erased once the testing of the chip is over. In that case, the DFT scheme has very little overhead (typically less than 1%). Otherwise, the test microcode lines remain as an overhead in the control memory. The method requires the addition of only one external test pin. Application of this technique to several examples has resulted in a very high fault coverage (above 99.6%) for all of them. The test generation time is about three orders of magnitude smaller compared to an efficient gate-level sequential test generator. The average area overhead (without assuming an erasable ROM) is 3.1% while the delay overheads are negligible. This method does not require any scan in the controller or data path. It is also amenable to at-speed testing.

Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fa...

This talk introduces Archipelago, a software-defined storage layer providing unified File, Image and Volume resources over an object-storage backend. We will focus on how it can enable efficient workflows for High-Performance Computing in a cloud environment. Archipelago is commonly deployed over Ceph's RADOS object store. With Archipelago, one can: (a) Maintain commonly-used data sets as snapshots and attach them as read-only disks or writeable clones in VMs running the application, (b) begin with a base OS image, bundle all application and supporting library code inside it, and upload it to the Archipelago backend in a syncing, Dropbox-like manner, (c) start a parallel HPC application in hundreds of VMs, thinly provisioned from this Image, (d) modify the I/O processing pipeline to enable aggressive client-side caching for improved number of IOPS, (e) create point-in-time snapshots of running VM disks, and sync them back to their PC for further processing. We conclude with the discussion of upcoming Archipelago features, including direct communication with the storage layer from a guest's userspace, and running Archipelago's shared-memory control and data path over Infiniband RDMA.

This paper presents a high-level synthesis methodology which may be applied to the synthesis of bit-serial, digit-serial or bit-parallel digital signal processing (DSP) systems. The methodology accepts as input a DSP system behavioral specification. The methodology provides for the optimization of DSP systems subject to constraints on throughput, IC area, data path width, and resource sharing strategies. The optimization technique is based on a generalized hill climbing algorithm known as simulated annealing. The output is control logic and data path specifications in a device independent hardware description language. Design examples of bit-serial and digit-serial filter realizations synthesized using the methodology are included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In the research on automatic generation of testing cases, there are different execution paths under drivers of different testing cases. The probability of these paths being executed is also different. For paths which are easy to be executed, more redundant testing case tend to be generated; But only fewer testing cases are generated for the control paths which are hard to be executed. Genetic algorithm can be used to instruct the automatic generation of testing cases. For the former paths, it can restrict the generation of these kinds of testing cases. On the contrary, the algorithm will encourage the generation of such testing cases as much as possible. So based on the study on the technology of path-oriented testing case automatic generation, the genetic algorithm is adopted to construct the process of automatic generation. According to the triggering path during the dynamic execution of program, the generated testing cases are separated into different equivalence class. The number of testing case is adjusted dynamicly by the fitness corresponding to the paths. The method can create a certain number of testing cases for each execution path to ensure the sufficiency. It also reduces redundant testing cases so it is an effective method for automatic generation of testing cases.

A basic CAD-tool using a simple grid-like floorplan for placement of cells of varying sizes is presented. It is focused on the generation of physical and behavioural descriptions of data paths but is also suitable for random logic, data path controllers containing PLA's, registers, counters etc. and for analog designs containing OP's, capacitors etc. Two different types of floorplans can be chosen; one resembling the standard cell design approach and one resembling the bit-slice approach. By not assembling the cells with abutment, existing general purpose cell libraries can be used. An easy modifiable interpreting lisp-like language is used as input. Three design examples are discussed, one data path for a decimation filter, one data path for a Viterbi receiver and one multiplier.