A high throughput variable length decoder with modified memory based architecture

In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 mum process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.

This paper presents a low-cost high-performance H.264/AVC SVC decoder with multi-symbol prediction context-based adaptive variable length coding (CAVLC) for advanced T-DMB receiver. Proposed multi-symbol prediction CAVLC mainly consists of a simple arithmetic operation unit with reduced look-up tables and a leading zero detector. We also propose a multi-symbol run_before decoder and it decodes more than 2.5 symbols in a cycle. Gate count of a H.264/AVC SVC decoder is about 1,300K gates when synthesized with 0.18 um CMOS process and it can be operated at 120 MHz clock frequency. For the verification of a H.264/AVC SVC decoder chip, prototype mobile movie player systems have been implemented using a 7 inch LCD and USB controller.

This paper describes an experiment which aims to reveal the potential impact on performance yielded by augmenting a TriMedia-CPU64 processor with a multiple-context FPGA core. We first propose an extension of the TriMedia CPU64 architecture, which consists of a reconfigurable functional unit and its associated instructions. Then, we address the decoding of variable-length codes on such extended TriMedia and describe the architecture and FPGA-implementation of a variable-length decoder (VLD) computing facility. When mapped on an ACEX EP1K100 FPGA, the proposed VLD exhibits a latency of 7 cycles. Preliminary results indicate that by configuring each of the VLD and 1-D IDCT (which is described elsewhere) facilities on a different FPGA context, and by activating the contexts as needed, the augmented TriMedia can perform macroblock parsing followed up by pel reconstruction with an improvement of 20 - 25% over the standard TriMedia.

Multivalued logic applications of heterostructure devices and circuitry

The rapid growth in wireless communication has caused an increased demand for high speed error control decoders with improved BER performance. Turbo codes, the Shannon limit approaching codes, use Max-log-MAP decoders as the component decoders in the iterative decoding process. The demand for high speed error control decoders has led to an increased interest in the design of hardware-secure Max-log-MAP decoders with high throughput and reduced area. This paper focuses on designing a high throughput Max-log-MAP decoder with reduced area and analyzing the effect of a run time triggered multinet connected Trojan on its performance. High throughput is achieved by using radix-4 and radix-8 architectures and area is optimized using maximum sharing of resources (MSR) architecture. This architecture uses a modified add-compare-select unit designed by effectively utilizing the relationship existing between the branch metrics. Trojan analysis is performed by inserting a run time triggered multinet connected Trojan and comparing its performance with the Trojan free decoder.

Real-Time Image Processing is the key work in robot vision. With the limitation of the hardware technique, many algorithm-oriented firmware systems were designed in the past. But their architectures were not flexible enough to achieve a multi- algorithm development system. Because of the rapid development of microelectronics technique, many high performance DSP chips and high density FPGA chips have come to life, and this makes it possible to construct a more flexible architecture in real-time image processing system. In this paper, a Double DSP General Image Processing System (DDGIPS) is concerned. We try to construct a two-DSP-based FPGA-computational system with two TMS320C6201s. The TMS320C6x devices are fixed-point processors based on the advanced VLIW CPU, which has eight functional units, including two multipliers and six arithmetic logic units. These features make C6x a good candidate for a general purpose system. In our system, the two TMS320C6210s each has a local memory space, and they also have a shared system memory space which enable them to intercommunicate and exchange data efficiently. At the same time, they can be directly interconnected in star- shaped architecture. All of these are under the control of FPGA group. As the core of the system, FPGA plays a very important role: it takes charge of DPS control, DSP communication, memory space access arbitration and the communication between the system and the host machine. And taking advantage of reconfiguring FPGA, all of the interconnection between the two DSP or between DSP and FPGA can be changed. In this way, users can easily rebuild the real-time image processing system according to the data stream and the task of the application and gain great flexibility.

This paper analyses the very high system throughput of IEEE 802.11ac by taking into consideration the key features of MAC and PHY layers under a Multiple In Multiple Out (MIMO) channel. Throughput at the MAC layer is calculated from the transmission probability, contention window and transmission stage. Likewise, the new critical attributes of 802.11ac PHY (i.e. modulation and coding schemes, spatial streams, and channel bandwidth) are used to determine the throughput at the PHY layer. To this end, a theoretical model is formulated at the MAC and PHY layers followed by a system model of MIMO multipath fading channel for 802.11ac. The system model is verified by simulation analysis. The results compare theoretical and simulation findings for different sets of parameters. Furthermore, important trends and trade-offs are identified between system throughput and (MAC + PHY) features as a function of number of contending stations and payload size. The system throughput of 802.11ac networks is significantly improved due to the addition of new PHY features. However, the system may degrade upto 50% in terms of symbol reception in case of a high error-prone MIMO channel. The performance of 802.11ac systems is also analyzed under different MIMO TGn channel models in terms of Packet Error Rate (PER). Thus based on our simulation results, an appropriate channel model can be chosen for 802.11ac network under a given configuration to achieve a better performance.

The function of the control unit of an electronic digital computer is to provide the sequences of pulses, which, when applied to the store, arithmetic unit and other units of the machine, cause the orders of the programme to be executed. The paper discusses a number of related ways in which a systematic and flexible design for a control unit may be achieved. In one group of systems the order code is determined by the arrangement of diodes in a diode matrix, and in another by the appropriate threading of wires through a matrix of ferrite cores. The first part of the paper is concerned with logical design, and the second part with the practical design of a system using a ferrite matrix.

본 논문에서는 <TEX>$GF(2^{163})$</TEX>타원곡선 암호 프로세서를 제안한다. 제안한 암호 프로세서는 타원곡선 정수 곱셈을 위해 수정된 Loez-Dahab Montgomery 알고리즘을 채택하고, <TEX>$GF(2^{163})$</TEX>상의 산술 연산을 위해 가우시안 정규 기저(Gaussian Normal Basis: GNB)를 이용한다. 높은 처리율을 위해 Lopez-Dahab 방식에 기반한 규칙적인 주소화 방식의 병렬 타원곡선 좌표 덧셈 및 배 연산 알고리즘을 유도하고 <TEX>$GF(2^{163})$</TEX>상의 연산을 수행하는 두 개의 워드-레벨 산술 연산기(Arithmetic Unit: AU)를 설계한다. 제안된 타원곡선 암호 프로세서는 Xilinx사의 XC4VLX80 FPGA 디바이스에 구현되었으며, 24,263개의 슬라이스를 사용하고 최대 동작주파수는 143MHz이다. 제안된 구조를 Shu 등의 하드웨어 구현과 비교했을 때 하드웨어 복잡도는 약 2배 증가 하였지만 4.8배의 속도 향상을 보인다. 따라서 제안된 타원곡선 암호 프로세서는 네트워크 프로세서와 웹 서버등과 같은 높은 처리율을 요구하는 타원곡선 암호시스템에 적합하다. In this paper, we propose a high performance elliptic curve cryptographic processor over <TEX>$GF(2^{163})$</TEX>. The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for <TEX>$GF(2^{163})$</TEX> field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over <TEX>$GF(2^{163})$</TEX> and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

Hardware design of a high speed and memory efficient Huffman decoder, introduced in(l), is presented. The algorithm developed is based on a specific Huffman tree structure using a code-bit clustering scheme. The method is shown to be extremely efficient in memory requirement, and fast in searching for symbols. For an experimental video data with code-words extended up to 13 bits, the entire memory space needed is shown to be 122 words in size, compared with normally 213 = 8196 words memory space re- quirement. The design of the decoder is carried out using silicon- gate CMOS process.

In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention by arbitrating memory access in such a way that competing threads progress at a relatively fast and even pace, resulting in high system throughput and fairness. Previously proposed memory scheduling algorithms are predominantly optimized for only one of these objectives: no scheduling algorithm provides the best system throughput and best fairness at the same time. This paper presents a new memory scheduling algorithm that addresses system throughput and fairness separately with the goal of achieving the best of both. The main idea is to divide threads into two separate clusters and employ different memory request scheduling policies in each cluster. Our proposal, Thread Cluster Memory scheduling (TCM), dynamically groups threads with similar memory access behavior into either the latency-sensitive (memory-non-intensive) or the bandwidth-sensitive (memory-intensive) cluster. TCM introduces three major ideas for prioritization: 1) we prioritize the latency-sensitive cluster over the bandwidth-sensitive cluster to improve system throughput, 2) we introduce a ``niceness'' metric that captures a thread's propensity to interfere with other threads, 3) we use niceness to periodically shuffle the priority order of the threads in the bandwidth-sensitive cluster to provide fair access to each thread in a way that reduces inter-thread interference. On the one hand, prioritizing memory-non-intensive threads significantly improves system throughput without degrading fairness, because such ``light'' threads only use a small fraction of the total available memory bandwidth. On the other hand, shuffling the priority order of memory-intensive threads improves fairness because it ensures no thread is disproportionately slowed down or starved. We evaluate TCM on a wide variety of multiprogrammed workloads and compare its performance to four previously proposed scheduling algorithms, finding that TCM achieves both the best system throughput and fairness. Averaged over 96 workloads on a 24-core system with 4 memory channels, TCM improves system throughput and reduces maximum slowdown by 4.6%/38.6% compared to ATLAS (previous work providing the best system throughput) and 7.6%/4.6% compared to PAR-BS (previous work providing the best fairness).

This paper presents the design and implementation of a pipelined 9-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. Harvard Architecture is used which has distinct program memory space and data memory space. The only load and store is used to communicate with data memory. RISC using pipeline makes CPI as 1 and improves speed of execution. Verilog Language is used for coding purpose. The proposed architecture is then simulated using Modelsim. Reduced Instruction Set Computers (RISCs) are now use for all type of computational tasks. In the area of scientific computing, RISC workstations are being increasingly used for compute task such as DSP, DIP etc. RISC concepts help to achieve given levels of performance at significantly lower cost than other systems. Pipelined RISC improves speed and cost effectiveness over the ease of hardware description language programming and conservation of memory and RISC based designs will continue to grow in speed and ability. The main features of RISC processor are the instruction set can be hardwired to speed instruction execution. In the present work, the design of a 4-bit data width Reduced Instruction Set Computer (RISC) processor is presented. It has a complete instruction set, program and data memories, general purpose registers and a simple Arithmetical Logical Unit (ALU) for basic operations. In this design, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. The architecture supports 8 instructions to support Arithmetic, Logical, Shifting, and load -store operations. Verilog HDL has evolved as a standard hardware description language. A hardware descriptive language is a language used to describe a digital system. HDL's allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology- independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description for the circuit. The simulator which is used for the language is Xilinx ISE and Modelsim. Verilog is capable of describing simple behaviour. Machine cycle instructions allow the processor to handle several instructions at the same time. The processor can work at a high clock frequency and thus yields higher speed. This paper is about design of a simple RISC processor and synthesizing it. The RISC architecture follows single-cycle instruction execution.

In the modern chip-multiprocessor system, main memory is a shared resource among multiple concurrently executing threads/applications. The memory scheduling algorithms are developed to resolve memory contention by arbitrating memory access in such a way that competing threads progress at a relatively fast and even pace, resulting in high system throughput and fairness. This paper presents a new memory scheduling algorithm called Time-Based Least Memory Intensive scheduling (TB-LMI) that addresses system throughput and fairness with the goal of achieving a better throughput and limiting the unfairness. The main idea is to prioritize threads according to their memory contentions every pre-defined period of cycles to improve system throughput and to guarantee fairness. We evaluate TB-LMI on a variety of multi-programmed workloads with different queue sizes of memory controllers and compare its performance to four previously proposed scheduling algorithms. TB-LMI achieves the best system throughput and fairness. On 8-core system, TB-LMI improves system throughput and fairness on average by 4.22% and 11.7% respectively compared to Thread Cluster Memory scheduling (TCM) (previous work providing the best system throughput and fairness). Our newly proposed technique adds negligible area and logic overhead to the Memory Controller compared to the benefits on the system performance.

Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. A 16 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx ISE 14.7 design suite. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. In addition to these blocks, designed RISC Processor consists of other blocks like Control unit and data path, Register Bank, Program Counter and Memory. The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that 44% savings in power in case of MAC and that of 12% in case of ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced by 45% in case of MAC and that of 35% in case of ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 16-bit Vedic processor is developed. This reduces the delay by 34% and saves around 88% power compared to conventional processor. Hence the improvement in speed of operation, reduction in power utilization and less area utilization are the key features of designed RISC processor.

In strobe addressing, a pulse from the memory drum or disk forces the control unit to accept a program word. Strobe addressing for drums or disks costs less than 20 per cent of conventional addressing for real-time control programs, but becomes impractical for very complex problems. A comparison of various forms of strobe and conventional addressing shows that simple strobe addressing uses the memory as efficiently as conventional addressing if the problem can and must be solved in one revolution. By interlacing instructions with complete freedom for the program to switch interlaces, a strobe-addressed drum appears to have as many parallel bands as it has interlaces, thereby extending the advantages of strobe-addressing to more complex problems. Only minor changes in the program memory are necessary, and the arithmetic element and control unit remain essentially unchanged. The irregular interlace organization is described for an airborne computer with an 8-fold interlace, and its effectiveness is evaluated. In a test problem, this method reduces the size of the required memory by a factor of four and increases the effective computing speed fourfold.